LHCb RICH pixel chip tests on behalf of pixel group

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LHCb RICH pixel chip tests on behalf of
pixel group
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Testing

• First tests on IC Tester (chips glued and
  wire-bonded to daughter-board)
• chip is fully functional - very encouraging!
• JTAG configuration works
• DACs work (see below)
• Front-end works
• Digital delay/FIFO/readout works
• Power consumption as expected
• Fast-OR, Fast-Multiplicity work
• No noisy pixels
• Rough idea of minimum threshold lt2000e-
• noise 200e-

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Pixel chip tests

• A few mysteries
• DACs give wrong default values
• Voltage DACs saturate at value lower than
  expected
• Clocking frequency of digital limited to 20MHz
• Gain of front-end not as simulated
• Unfortunately, time on IC tester is limited
• too many different chips arrived at the same
  time!!

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Tests recent progress

• VME-based lab system now complete in ALICE lab
  (PILOT, JTAG controller, motherboard)
• PC (labview) control
• gt allows systematic measurements of chip
  parameters
• System being copied in LHCb lab
• Some mysteries solved
• DAC default values simulation problem
• Voltage DAC saturation due to parasitic loading
• Front-end gain inefficient generation of test
  pulse - low amplitude
• Clocking limit a hypothesis from measurements
  to be investigated

• Work plan full, systematic tests of chip
• threshold scans
• timewalk
• parameter sensitivity
• radiation
• probe station
• AND try to solve the mysteries..!!!!
• De-bug LHCb system and prepare for different
  stages leading to tube testing

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Question on verification

• Problems with checking (DRC) before sending to
  IBM
• New software (HERCULES) is now available for
  checking.
• Same software used at IBM.
• Software will be fully tested on MEDIPIX design -
  submission next month.
• Should result in significant time saving!!!