Model Order Reduction for Large Scale Dynamical Systems Lecture 10: Analog Simulation in IC Industry

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Model Order Reduction for Large Scale Dynamical
SystemsLecture 10 Analog Simulation in IC
Industry Implementation of the Multirate
Algorithm
NXP Semiconductors
Bratislav Tasic
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Content

• Introduction
• In-house NXP Simulator Pstar
• Speeding-up Analog Simulation
• Multirate Concept and Prototype
• Limitations
• Architecture
• Dynamical Partitioning
• Current Version and Future Plans
• Example
• Conclusions

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IC Business
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Introduction

• Modern circuit simulation
• Larger and more complex designs (hundreds to
  millions unknowns)
• Various typical dynamical behaviour (various
  frequencies, analog, digital, thermal, etc.)
• Fast yet accurate analyses needed (transient in
  particular)
• Typically more than one time-scale involved
  Partitions (e.g. high/low frequencies, analog and
  digital)
• Professional software EDA vendors or in-house
  tools

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Direction of Top 10 Semiconductor Houses

• In top-10 semiconductor houses gt70 has in-house
  analogsimulation competence
• Intel, TI, Freescale, NEC, ST, Infineon, Qimonda,
  NXP, IBM
• In top-10 analog semiconductor houses all have
  in-houseanalog simulator
• Infineon/Qimonda Titan, ST Eldo, Intel Lynx
  and Mynx, NXP Pstar
• In-house analog sim. competence offers
• Proven track record
• Predictable costs
• Competences adapted to business needs
• Tightly integrated organisation
• Shared knowledge of design andmanufacturing
  issues
• For nano-scale design trend is for morein-house
  EDA development

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Pstar is Robust Design

• Statistics
• More capacity than any commercial tool
• 2x overall faster statistical analysis
• Statistical results directly available
• no manual post-processing needed
• World class statistical modeling
• Stability analysis
• For Voltage Regulators, Automotive, Power Amps
• Using best-in-class pole-zero analysis methods
• Assure stability for varying load conditions
• Reliability simulation
• Alliance NBTI solution built on Pstar experience

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Pstar is System Design

• Top-Down System Design
• Run system-level simulation togetherwith
  circuit-level implementation
• Using MATLAB or Simulink for system-level
• System can be mixed domain(electrical,
  mechanical, thermal)
• MEMS, automotive
• Time-accurate solution for Simulink-circuit
  simulation
• No other (commercial) solution can handle
  feedback
• Analog Behavioral Modelling
• Verilog-A standard analog HDL

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Pstar is Analog Design

• Parametric simulations
• Including design-of-experiments (process-case)
• Integrated post-processing
• Simply build standardized tests for circuit
  performance
• Simple pass/fail analysis
• Reuse of test-benches for similar designs
• Analog diagnosis
• Fast and easy access to all simulation data

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Pstar is Innovation

• Enables NXP Research efforts for world-class
  device models
• CMC world standards (PSP, Mextram, Juncap2)
• Proprietary models (FinPSP)
• Invaluable in fast characterization

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Transient Simulation

• Transient analog simulation
• Most expensive
• Solving systems of DAEs
• Highly involved, complex and expensive simulation
• Circuits
• Becoming larger daily
• More difficult to simulate
• Application areas
• Analog circuits
• Mixed systems (for simulating the analog part)
• Statistical runs

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Transient Simulation

• Network models of electrical circuits
• Network models consisting of nodes and branches
• Kirchhoffs Laws and constitutive branch
  equations
• ib, vb branch currents/voltages vn
  nodal voltages
• Modified Nodal Analysis
• One voltage has to be grounded
• Hierarchical structure

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Transient Simulation

• Solving IVP
• Implicit A(?)-stable numerical time-integration
  scheme, e.g. variable order BDF (costly)
• How to increase the simulation speed preserving
  the accuracy?

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Transient Simulation

• High-speed simulators
• HSIM, UltraSim, etc.
• Fast, yet sometimes not accurate enough
• Switching from on to other simulators is not easy
• Golden simulators
• Pstar, Spectre, HSPICE, ADS, Titan, etc.
• Requests from IC designers
• Speedup the transient analysis runs
• Preserve the accuracy and the robustness
  Preserve the golden standard
• No significant extra effort required to run the
  simulation

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Mathematical Background

• Speedup approaches
• Table modeling
• Model order reduction
• Parallel computation
• Isomorphic matching
• Multirate numerical integration methods
• Table modeling
• Interpolation technique to avoid evaluation of
  expensive models
• Model order reduction
• Still under theoretical development and
  validation especially for nonlinear problems

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Mathematical Background

• Parallel computation
• More and more popular (prices of clusters are
  becoming reasonable and some math. libraries
  already available)
• Seems suitable for hierarchical solver
• It could be perfect for statistical runs
• Isomorphic matching
• Storing repeated instances of the same circuit
• Strong advantage of the hierarchical solver
• Power behind Hsim
• Not always accurate (e.g. wakeups)

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Mathematical Background

• Multirate numerical integration methods
• Suitable for circuits where large part of the
  circuit is latent (slow) during the simulation
  (sub)intervals
• The best candidate to achieve significant speedup
• The accuracy and robustness can be preserved
• Still under development improvements are still
  to be expected in future
• Compound-Fast algorithm
• New and fully developed algorithm that shows
  improved stability and robustness results as
  compared to standard multirate technique (no
  extrapolation involved) PhD work of Arie
  Verhoeven

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Multirate Methods

• Multiple time scales Multiple time steps
• Latent parts Coarse time grid
• Active parts Refined time grid
• Faster overall progression in time Speedup
  factor

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Concept
Transientanalysis
Multirateprototype
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Concept
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Concept
Standard transient
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Concept
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BDF Compound-Fast Multirate Method

• Mappings necessary to partition the circuit
• Solving modified IVP

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BDF Compound-Fast Multirate Method

• Algorithm
• Compound step (relaxed Newton process)
• Interpolation of the interface
• Refinement phase

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Adaptive Multirate Step Size Control

• Local truncation errors (LTEs) should satisfy
• Computing LTEs using extrapolation polynomials
  based on BDF history and computed solutions

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Adaptive Multirate Step Size Control

• Computing Hn1 (interpolation error included)
• Computing hn-1,m1

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Examples
Non-linear chain
Speed up factor 11 Ratio 99.93 - 0.07
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Examples HSOTA
Speed up factor 1.6 - 2 Size Ratio 50
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Examples Charge Pump
Speed up factor 5 Ratio 12
FAST
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Examples
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Dynamical Partitioning

• Time stepping

Prototype static partitioning
Multirate with dynamical partitioning
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Dynamical Partitioning
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Dynamical Partitioning
t T2
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Dynamical Partitioning

• Speedup factor estimation
• Optimization problem maximizing S

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Example

• The nonlinear chain with more FAST models

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Example

• Results

S unknown F1 unknown F2 unknown Refine S Refine
F1 Refine F2
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Example

• Performance comparison
• RR models 5000, f1/f2 500

Results obtained for the static test cases are
almost exactly the same regarding the CPU time
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Conclusions

• Multirate transient analysis based on dynamical
  partitioning shows great potential highly user
  friendly
• Current prototype shows good results and a
  potential to improve
• Several partitioning algorithms have been
  investigated and implemented
• Search for the realistic design examples to
  determine in which areas the multirate potential
  is largest

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Thank you