SiW Testbeam

1
SiW Testbeam
Active Groups
M. Breidenbach, D. Freytag, N. Graf, G. Haller,
A. Kujawinska, T. Nelson SLAC Electronics
Mechanical Design Simulation
V. Radeka BNL Electronics
R. Lander, M. Tripathi UC-Davis Bump
Bonding Mechanical Design Cabling
R. Frey D. Strom UO Si Detectors Mechanical
Design Simulation
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Planned SiW Module

• One wafer/layer
• 750 pixels/layer
• 30 layers
• 2.5mm and 5mm W

3
Status of SiW Hardware
Detectors

• 10 Si Detectors procured
• At least 20 more Si detectors must be purchased
• 30 Tungsten plates procured

Electronics

• 64 prototype chip to be submitted soon (within
  months)
• At least thirty 1024 channel chips needed for
  test beam
• This quantity of large chips requires expensive
  dedicated production run

First step will be to test bump-bonding with 64
channel chip
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Many important details are still to be defined

• Mechanical design of test beam module
• Cables for 1024-channel chip
• Readout of 1024-channel chip
• Bias scheme for test beam wafers
• Temperature monitoring and cooling

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Electronics implication on Test Beam Requirments

• A test beam with the same time structure as the
  LC would be ideal (3000 bunches at 5 Hz)
• Readout chip clock can be adjusted to match time
  structure of test beam (150ns to 1000ns)
• Effective length of bunch train can not be
  extended much beyond 1ms
• Digitization and readout time for electronics
  chip (without zero suppression) will be 6ms
• Implies 15 live time for slow spill
  operation