Architectural Evaluation of Flexible Digital Signal Processing for Wireless Receivers

1
Architectural Evaluation of Flexible Digital
Signal Processing for Wireless Receivers

• Ning Zhang and Robert W. Brodersen
• Berkeley Wireless Research Center

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Outline

• Motivations
• Reconfigurable architectures
• Function-specific reconfigurable hardware design
  and evaluation methodology
• Design example an OFDM receiver
• System level requirements for flexibility
• Energy efficiency and computation density
  comparison
• Conclusions

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Wireless Communications System Design

• System requirements
• High performance
• High capacity
• High data rate
• Flexibility
• Diverse and evolving application requirements
• Changing parameters of the available
  communication link
• Low energy consumption
• Mostly digital receiver
• CMOS technology scales as Moores Law predicted

• But

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Shannon Beats Moores Law and Energy Plays a
Major Role
Source Jan Rabaey, Summer Course, 2000
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Architectural Choices
Flexibility
1/Efficiency
0.1-1 MOPS/mW
100-1000 MOPS/mW
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Software On DSP

• Examples
• High performance TI C6x
• Low power TI C5x
• Speed and energy results are based on assembly
  benchmarks and power measurements published by
  the vendor

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Reconfigurable Logic FPGA

• Example
• Xilinx Virtex-E
• Use CORE Generator system
• Results are from post-layout timing analysis and
  power estimation tools

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Reconfigurable Data-Path

• Example
• Chameleon Systems CS2000
• Results are based on preliminary measurements
  and estimates

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Function-Specific Architecture

• Application and algorithm level
• Focus on wireless communications transceiver
  signal processing
• Minimize the hardware reconfigurability to a
  constrained set
• Identify computational kernels
• Architecture level
• Exploit algorithms structure
• Choose modular and scalable architecture
• Circuit level
• Apply low-power design techniques

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Evaluation Methodology

• Module design
• Data-path synthesis
• Post-layout delay, energy and area
  characterization
• Implementation estimation
• Critical path delay
• Choose supply voltage for lowest energy-delay
  product
• Estimate loading of each block
• Energy (Power)
• Combine switching activity with average energy
  consumption
• Add glitching overhead
• Area
• Floor-plan modules

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Design Example
Add cyclic
Convolutioanl

IFFT
Windowing


prefix
encoder


Transmitter

Multi-path channel

Receiver
-
Synchroni- zation
Channel
Viterbi

FFT

estimation
decoder

• Desired Flexible Parameters
• FFT
• size and input sample rate
• Viterbi decoder
• constraint length, survivor path length,
  puncturing rate and decoding rate

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Shuffle-Exchange Network
FIFO
FIFO
FIFO
4
2
1
PE3
PE2
PE1
clk
PE3
work
bypass
PE2
work
work
bypass
bypass
PE1
bypass
work
bypass
work
bypass
work
bypass
work
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FFT and State Metric Update
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Survivor Path Memory
One-pointer trace-back with single-port SRAM
b x
N256
N128
N64
N32
N16
Cycles for each state metric update
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16/7
4/3
4/5
1/2
b
1
2
2
5
6
D
L/2
7L/18
3L/2
5L/2
L
L
48
36,72, 108
2k k lt 48
6k k lt16
12k k lt 16
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Architectural Implementation Comparison FFT
Energy per Transform vs. FFT size
Transforms per Second per mm2 vs. FFT size
All results are scaled to 0.18mm
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Architectural Implementation Comparison Viterbi
Decoder
Energy per Decoded Bit vs. Number of States
Decoding Rate per mm2 vs. Number of States
All results are scaled to 0.18mm
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Summary

• System, architecture and circuit design need to
  be considered together to provide
  high-performance and flexibility with low-power
  consumption required for future wireless
  receivers
• Function-specific reconfigurable architecture
  takes the application-specific leverage and
  supports sufficient flexibility
• Design examples (FFT and Viterbi decoder) show
  2-3 orders of magnitude higher energy efficiency
  and computation density than can be achieved by
  other reconfigurable architectures