ELEC 59700016970001Fall 2005 Special Topics in Electrical Engineering LowPower Design of Electronic

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ELEC 5970-001/6970-001(Fall 2005)Special Topics
in Electrical EngineeringLow-Power Design of
Electronic CircuitsPower Analysis Probability
Waveform

• Vishwani D. Agrawal
• James J. Danaher Professor
• Department of Electrical and Computer Engineering
• Auburn University
• http//www.eng.auburn.edu/vagrawal
• vagrawal_at_eng.auburn.edu

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Digital Signal Waveforms
Transient region
Primary Inputs
Gate Outputs
time
Clock period
3
Transient Events
Path P1
1 3
1
0
2 4 6
P2
1
2
3
0
P3
5
2
0
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Probability Waveform
Vector period
Samples of signal, s(t)
Transient interval
Steady state
time
0
Next input vector applied
Input vector applied
Transition probabilities
0.25
1.0
0.25
0.5
0.5
P(t) 0.25
P(t)0.25
Prob. waveform, P(t)
time
0
0.5
0.5
0.25
0.25
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Probability Simulation
010101010101
1
1
001100110011
2
3
000111000111
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Primary Input Pattern Analysis
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PI Waveforms
0.5
PI 1
time
0 1 2 3 4 5 6 T
0.5
PI 2
time
0 1 2 3 4 5 6 T
PI 3
0.5
time
0 1 2 3 4 5 6 T
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Probability Simulation
0.25
0.5
PI 2
0.25
time
0 1 2 3 4 5 6 T
0.2085
2
PI 3
0.75
0.2085
0.167
time
0.5
0 1 2 3 4 5 6 T
0.167
time
0 1 2 3 4 5 6 T
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Probability Simulation
0.5
0.5
0.375
0.10425
0.5
0.375
0 1 2 3 4 5 6 T
0.10425
0.375
PI 1
0 1 2 3 4 5 6 T
1
1
0.2085
3
0.2085
0.75
0.25
0.2085
time
0 1 2 3 4 5 6 T
0 1 2 3 4 5 6 T
0.2085
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Probability Simulation
0.375
0.10425
0.375
0.375
0.10425
0 1 2 3 4 5 6 T
1
0.1303125
0.0781875
0.28125
0.2085
0.53125
0.25
0.28125
0.0781875
0.1303125
0 1 2 3 4 5 6 T
0 1 2 3 4 5 6 T
0.2085
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Power Consumption of a Gate

• An input change can multiple transitions at the
  output of a gate.
• Per vector power consumed by a gate

CV2 S p01(ti) ti e 0,T
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Methods Related to Probability Waveform

• Tagged probability simulation (TPS) Four
  waveforms corresponding to steady states, 00,
  01,10 and 11, are explicitly simulated.
• Dual-transition simulation (Dual-Trans) An
  improvement of TPS that considers pairs of
  consecutive transitions and gate delay to filter
  glitches.
• Further improvement is possible with supergate
  analysis to account for signal correlation.

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References

• F. Najm, R. Burch, P. Yang and I. Hajj, CREST
  A Current Estimator for CMOS Circuits, Proc.
  IEEE Int. Conf. on CAD, Nov. 1988, pp. 204-207.
• C.-S. Ding, et al., Gate-Level Power Estimation
  using Tagged Probabilistic Simulation, IEEE
  Trans. on CAD, vol. 17, no. 11, pp. 1099-1107,
  Nov. 1998.
• F. Hu and V. D. Agrawal, Dual-Transition Glitch
  Filtering in Probabilistic Waveform Power
  Estimation, Proc. IEEE Great Lakes Symp. VLSI,
  Apr. 2005, pp. 357-360.
• F. Hu and V. D. Agrawal, Enhanced
  Dual-Transition Probabilistic Power Estimation
  with Selective Supergate Analysis, Proc. IEEE
  Int. Conf. Computer Design, Oct. 2005. pp.
  366-369.

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Power Estimation by Prob. Waveform