Clockless Logic

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Clockless Logic

• Montek Singh
• Tue, Mar 23, 2004

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Outline

• Classic static logic pipeline Sutherland
• Classic dynamic logic pipeline Williams/Horowitz

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A Classic AsynchronousDynamic Pipeline

• Williams and Horowitzs PS0 pipeline
• Structure
• Operation
• Performance

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A Classic Approach PS0 Pipeline

• Williams/Horowitz (Stanford U.) 1986-91
• successfully used in fabricated chips Stanford
  87 HAL 90s

Implemented using dynamic logic
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PS0 Pipeline Stage

• A PS0 stage consists of dynamic gates and a
  completion detector

PC
keeper
datainputs
Pull-down network
dataoutputs
Processing Block
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Dual-Rail Completion Detector

• Combines dual-rail signals
• Indicates when all bits are valid (or reset)

• C-element
• if all inputs1, output ? 1
• if all inputs0, output ? 0
• else, maintain output value

• OR together 2 rails per bit
• Merge results using C-element

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PS0 Protocol

• PRECHARGE N when N1 completes evaluation
• delete data after next stage has copied it
• EVALUATE N when N1 completes precharging
• accept new data after next stage is emptied

indicates done
indicates done
N
N1
N2
precharges
evaluates
evaluates
evaluates
Complete cycle 6 events
Precharge ? Evaluate another 3 events
Evaluate ? Precharge 3 events
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PS0 Performance
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Summary PSO Pipelining

• Datapaths are latch-free
• dynamic gates themselves provide implicit latches
• chip area savings
• extremely low latency
• Data items kept separate by control
• stage deletes data only after next stage has
  copied it
• stage accepts new data only if next stage is
  empty
• distinct data items always separated by spacers
• Control is extremely simple each controller
  single wire
• completion detector directly controls previous
  stage
• chip area savings
• low control overhead

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Comparison to a Clocked Pipeline

• How would you design the pipeline if you actually
  had a clock?
• Replace handshaking with magic clocking
• each stage gets its own clock
• successive clocks are slightly skewed
• essentially, clocked simulation of asynchronous
  handshaking!
• need multiple clock phases!

Ck
Ck

• Use a single clock, but insert latches between
  stages
• latches are simple, level-sensitive
• consecutive stages receive complementary clock
  signals

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Comparison (contd.)

• Cycle Times?

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Drawbacks of PSO Pipelining

• Poor throughput
• long cycle time 6 events per cycle
• data tokens are forced far apart in time
• Limited storage capacity
• max only 50 of stages can hold distinct tokens
• data tokens must be separated by at least one
  spacer
• Our Research Goals address both issues
• still maintain very low latency