CS 161Computer Architecture Chapter 5 Lecture 9

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CS 161Computer Architecture Chapter 5Lecture 9

• Instructor L.N. Bhuyan
• www.cs.ucr.edu/bhuyan
• Adapted from notes by Dave Patterson(http.cs.berk
  eley.edu/patterson)

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Where We Are Machine Organization
Chap 5 2 weeks
Chap 6 1 week
Chap 7 3 weeks
Personal Computer
Computer
Processor (CPU)
Devices
Input
Control (brain)
Memory
Arithmetic-Logic Unit(ALU)
Datapath (brawn)
Output
Processor Chaps. 5 NOW
Chap. 8
Chap. 7 (done)
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MIPS-lite processor

• Want to build a processor for a subset of MIPS
  instruction set (MIPS-lite)
• just enough to illustrate key ideas
• instruction set subset (3 groups)
• arithmetic-logical add, sub, and, or,
  slt
• memory reference lw, sw
• control flow j, beq
• can we write real programs with just these?
• Need up to 5 steps to execute any instruction in
  our subset
• Step 1 fetch instruction Step 2-5 ?

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Instruction Execution Steps
Instruction Fetch

• 1. Read IMPC
• 2. Instruction Decode, PC PC 4, Register read
• ALU operation, Branch address computation
• LW/STORE in Data memory
• Register Write

Decode, Inc PC and Read Registers
ALU Operation, Branch address
Data Memory operation
Write Back
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building a Datapath for MIPS (step 1)
Memory

• Need up to 5 steps to execute any instruction
• Step 1 fetch instruction

. . . PC-4PCPC4PC8 . .
. . . add t0,t0,t0 add t0,s1,t0 lw
t1,20(s0) sw t1,4(t0) . .
Flow of execution
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Datapath Step 1 any instruction
A d d
4
32-bit adder or ALU wired only for add
PC
ReadAddress
Instruction
Once program is loaded, Imem is read-only
Clock
Imem
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building a Datapath for MIPS (step 2)

Memory(instruc-tion)
Step 1
add t0,s1,t0
R
0 17 8 8 0
32
op rs rt rd shamt funct
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Datapath Step 2 any instruction
R
add t0,t1,t2
op rs rt rd shamt funct

ReadRegister 1
Readdata 1
ReadRegister 2
Instruction
Readdata 2
WriteRegister
RegisterFile
WriteData
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RegWrite (write enable control point)
Control
Datapath Control Points
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Up to 5 Steps in Executing MIPS Subset

• 3rd step onwards depends on instruction class
• EX for ALU instructions, add t0, t1, t2
  outputs from registers t1 and t2 will be sent to
  the ALU input.
• For Memory-reference instruction Address ? Base
  offset lw t0,20(s0)

A L U
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building a Datapath for MIPS (lw step 3)
Memory(instruc-tion)
A L U
lw t0, 20(s0)
op rs rt address
I
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Datapath Step 3-4 R-format Instructions
add, sub, and, or, slt
ALU control
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ReadRegister 1
Readdata 1
t1
A L U
Zero
ReadRegister 2
Instruction
Result
Readdata 2
WriteRegister
t2
WriteData
Registers
RegWrite
t1 _at_ t2
32
, -, AND, OR, etc.
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Datapath Step 3 Branch
beq t0,t1,loop
PC 4 from step 1 datapath
A d d
ALU control
ReadRegister 1
3
Branchtarget
Readdata 1
t0
Instruc- tion
A L U
ReadRegister 2
Result
t1
Zero
Readdata 2
WriteRegister
To branch controllogic
Mult by 4
WriteData
Registers
RegWrite
SignExtend
32
16
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Datapath Step 3 Branch
beq t0,t1,loop
PC 4 from step 1 datapath
A d d
ALU control
ReadRegister 1
3
Branchtarget
Readdata 1
t0
Instruc- tion
A L U
ReadRegister 2
Result
t1
Zero
Readdata 2
WriteRegister
To branch controllogic
Mult by 4
WriteData
Registers
RegWrite
SignExtend
32
16
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building a Datapath for MIPS (lw step 4)
Memory(instruc-tion)
A L U
Memory (data)
Step 1
Step 4
. . .add t0,t0,t0 add t0,s1,t0 lw
t1,20(s0) sw t1,4(t0) . .
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Up to 5 Steps in Executing MIPS Subset

• 4th step depends on instruction class
• Ex for lw Fetch Data from MemoryData ?
  MemAddress
• For sw Put the contents of a register in Memory

Memory (data)
A L U
To register for LW
From Register for SW
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Up to 5 Steps in Executing MIPS Subset

• 5th step only for lw rest are done
• EX for lw Write Result Regrt ? Data

A L U
Memory (data)
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Datapath Step 3-5 Load/Store
lw t0,24(s3)
ALU control
op rs rt address
MemWrite
ReadRegister 1
Readdata 1
s3
Zero
Instruc- tion
A L U
ReadRegister 2
Readdata
s324
Address
24
Result
Readdata 2
WriteRegister
Dmem
WriteData
Registers
WriteData
RegWrite
SignExtend
MemRead
16
32
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Compose Datapath R-form Load/Store
Add muxes
ALU control
MemWrite
3
ReadRegister 1
Readdata
Readdata 1
Instr- uction
Zero
A L U
ReadRegister 2
MemTo- Reg0R-form1L/S
Address
Readdata 2
WriteRegister
M u x
Dmem
Registers
WriteData
WriteData
1 M u x 0
RegWrite
ALUSrc 0 R-format1 Load/Store
MemRead
SignExtend
32
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