Electronics Packaging Trends

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ElectronicsPackaging Trends

• by
• Reza Ghaffarian, Ph.D.
• NASA/Jet Propulsion Laboratory
• California Institute of Technology
• [phone]
• Reza.Ghaffarian_at_JPL.NASA.Gov

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Acknowledgment
The research described in this publication is
being conducted at the Jet Propulsion Laboratory,
California Institute of Technology, under a
contract with the National Aeronautics and Space
Administration. The author would like to
acknowledge continuous support of colleagues at
JPL/industry. The author extends his appreciation
to program managers at NASA Electronic Parts and
Packaging Program (NEPP) including M. Sampson
K. LaBel, Dr. C. Barnes, and P. Zulueta for their
managerial support.
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Outline

• Electronics Trends
• Package Types
• Device Function - Current Future
• IC Package
• Package Level (SIP) vs Device Level (SOC)
• Package Shrink- BGA/CSP
• 3D Stack COTS/High Reliability
• Mixed technology approach
• Low Pitch/High I/Os Package Challenges
• Summary

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Functionality Increase

• Decrease Chip Size
• Moore law
• Add Additional Function on Chip
• SOC (systems-on-chip), More Moore
• Shrink Package
• BGA, CSP, WLP, Flip chip
• Stack Package- Add of the Same
• 3D dimension using die/package (MCP- Memory only)
• Stack Package - Add of Different
• SIP - Memory logic
• More than Moore, SOP (systems-on-package)-
  SIP/Optic/MEMs
• Nanotechnology
• Near future Top down, e.g. Carbon
  nanotubes/nanowires
• Future Bottom up, e.g. Molecular electronics,
  DNA, Quantum

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Moore's Law Increase in Heat
J Maix, MRQW2006
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Heat Affects Package Reliability
B. Jalali, UCLA
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Heat Degrades Solder Joint Reliability
40C Temp Rise
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More Function in IC Device -- SOC

• Si complexity
• Moores Law
• Every 3 years quadruples
• Core parameters increase
• Previously- Functionality, delay, power,
  testability
• Today- Signal integrity, electromigration,
  packaging effects, RF analysis
• Software complexity
• Embedded software
• Higher increase than Moore Law
• SOC
• Much higher complexity (Si Software)

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SOC Structure
Memory Flash
Memory SRAM/DRAM
PLL (Phase-locked loop)
Microprocessor Microcontroller cores
Interface Cores PCI, USB, UART
Glue Logic
TAP
Functional Specific Cores, DSP, 2D/3D graphics
A/D, D/A Convertors
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More IC Devices in a Package

• Stacking
• Bare die
• Peripheral wire bond, edge conductor connection
• Area arrayflip chip, stack with wafer using
  filled via
• Multichip Module (MCP)
• Conventional packages
• Peripheral lead
• Bare die stack
• Chip scale package
• Peripheral
• Bare die stack in CSP
• CSP stack
• Package shrink

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Package Trend TH to SM
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Package Shrink
MCP 62
2 CSP
Stack CSP
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CSP vs Flip Chip
Flip Chip 60 I/O
CSP 60 I/O
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Key Element of SIP Technology

• System partitioning/modularization
• Chip-package co-design (on-chip, off-chip)
• Integration of different functions in one package
• Application of add on technologies to increase
  system functionality
• High dense component integration
• Known good die
• Test and reliability
• Short time to market cycles
• Low Cost

Source ITRS 2005
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SIP- 3 Levels
MCM-MCP
SIP
SOP-MtM
Source ECTC 2006, D.Q Zhang, et all, Philips
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SOC vs SOP Cost/Profit
Source ITRS 2005
Source Suga, University of Japan
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SIP
Grid Arrays
Leads
Leaded
Stack CSP
MCP
Mix

• Low I/Os
• Conventional Assembly
• Heat Dissipation ?
• Reliability?

• High I/Os
• Large die, Reliability?
• Assembly Robustness

Self Alignment
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3D Die Stacking
3 Die Stack
Stacked Die
2 Die Stack
4 Die
3 Die
More Die in Smaller Packages
2 Die
1.0mm Thick
1.2mm Thick
1.4mm Thick
Courtesy S. Greathouse, Intel
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JPL 3D Package Stack Development
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3D Package for High Reliability Applications
C. Val, 3D Plus Presentation
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3D Package for High Reliability Applications
Maxwell, MRQW Presentation
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WB-SM for Extreme Cold Applications
IEEE, 2006, JPL TCRE Team
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Pkg Trend Low Pitch/High I/O Pb-Free Pb
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Adress Assembly Reliabity Issues
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Assembly Chalenges - Various Pkg Types/Pitches
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Effect of TC Profile on Pb-Free/Pb
IPC 9701A- Reza Ghaffarian
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References
http//NEPP.nasa.gov
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Summary

• IC size decrease
• Moore law
• Impossible in near? future, but CMOS in use
• IC functionality increase
• SOC (systems-on-chip), More Moore
• Complex, time-to-market- sub-system, less
  attractive than 3D/SIP/SOP/MtM
• Package shrink
• BGA, CSP, WLP, Flip chip
• Continue to increase I/O, WLP in use now
• Stacking- Increase of the same
• 3D dimension using die/package (MCP- Memory only)
• Widely used in various forms, continuous increase
  in number of stacks
• Functionality- Increase of different
• SIP - Memory logic
• More than Moore, SOP (systems-on-package)-
  SIP/Optic/MEMs
• iNEMI/ITRS roadmaps, more cost-effective
  faster-to-market systems
• Nanotechnology Much activities, patents
• Near future Top down, e.g. Carbon
  nanotubes/nanowires

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Insertion Qual Tailored for NASA Missions
NEPP Electronics Packaging tasks were leveraged
to support MER Hardware Thermal Design and
Environmental Verification Processes
New Packaging Qualification Verification Plan
(D-18799) developed to specifically address
electronics packaging
Applicable Requirements and Standards Flight
Project Practices, 6.13 Design Verification
for Environmental Compatibility (Doc ID
58032) Assembly Subsystem Level Environmental
Verification, 6.0 Thermal Verification (Doc ID
60133) Spacecraft Design Fabrication
Requirements (D8208, Doc ID 35120) Electronic
packaging systems shall be qualified by test to a
fatigue life margin of three
PQV Process Flow first considers heritage data in
the decision to conduct testing
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Insertion PQV for Heritage/New
Step 1
Develop Life Cycle Requirements
Subcontract Issued
Step 2
Packaging Technology Identification
No
Step 3
Is Heritage Data Available?
Yes
Step 5
Package Design ID Evaluation Phase
Time line
No
Is Heritage Data Applicable?
Step 4
Yes
No
Is Life Adequate?
Step 6
PDR
Yes
Generate List of Qualified Packaging Designs
For This Mission
Step 1
Step 7
CDR
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Insertion PQV for Heritage/New
NHB 5300.4 (3A-1), 200 cycles 55/100C NHB
5300.4 (3A-2), Do the right qualification
test Number of cycles 3 (ground mission)
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Risk Reduction- Packaging

• Package Trend
• Review industry roadmaps
• Active in industry
• Fund/managerial support (e.g. NEPP)
• Leverage
• High reliability
• Commercial industry if required
• Understand generic issues on quality/reliability
• Additional evaluation for specific needs
• Get involve early in design