Large gate periphery InGaAsInAlAs pHEMT: Measurement and Modelling for LNA fabrication

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Large gate periphery InGaAs/InAlAs pHEMT
Measurement and Modelling for LNA fabrication

• B. Boudjelida, A. Sobih, A. Bouloukou, S. Boulay,
  J. Sexton, T. Tauqueer, J. Sly and M. Missous
• School of Electrical and Electronic Engineering
• University of Manchester

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OUTLINE

• GOALS
• Low Fmin
• Low Rn
• ACTIVE DEVICES
• INTRINSIC PROPERTIES
• MODELLING
• RESULTS
• LNA SIMULATIONS
• QUICK ADC UPDATE
• CONCLUSIONS

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Workflow at University of Manchester
LNA building blocks library
LNA testing
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GOALS
Low Fmin and Low Rn

• Four noise parameters
• Fmin the minimum noise factor expected when Gs
  Gopt,
• Rn the equivalent noise resistance,
• Gopt and Bopt the real and imaginary parts of
  the optimal source admittance
• Yopt, for which

? For Broad band low noise amplification Need
both low Fmin AND low Rn
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GOALS
Low Fmin and Low Rn
Variation of Noise Resistance Rn with frequency
and temperature.
Variation of Fmin with frequency and temperature.
(NGST 0.1 x 80 um InGaAs-InAlAs Phemt )
Very difficult to achieve low Rn with submicron
devices below 2GHz
M.R. Murti et al. IEE Transactions MTT
48(12), 2579, (2000).
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ACTIVE DEVICES
Increased gate metallisation thickness
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The gate metallisation resistance key
contributor to gate resistance
For a fixed gate length increasing gate
thickness (h) reduces Rg
Why reduce it?
Key parasitic contributor
Comparison between VMBE1841 transistors made
with different gate metallisations (1x200µm
devices, Rg extracted, NFmin calculated for k3.6)
1 G. Vasilescu, Electronic noise and
interfering signals, Springer-Verlag Berlin
Heindelberg New York, 2005
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ACTIVE DEVICES
Latest results on Rg and Rn
Rg and Rn extracted from linear and non-linear
models, respectively.
Normal trend for 2-finger devices shows an
increase in Rg with increasing gate size
Rn decreases with increasing gate size
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ACTIVE DEVICES
Non Linear Modelling
EE-HEMT model generated from IC-Cap
measurements ? Transferred to ADS and fitted to
measured data
DC Characteristics Fit the Data very well ? Kink
effects not included in the model
RF Data (4x200 µm)
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LNA SIMULATIONS

• The use of large inductors (generally used for
  input matching) on MMIC
• Large space on chip
• Generate significant series resistance which
  greatly increases the noise figure

No input matching? Off-chip components?
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LNA SIMULATIONS
Single stage LNA (800 um gate width) with no
input matching
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LNA SIMULATIONS

• _at_ 1.4 GHz
• NF lt 0.6dB

Single stage LNA (800 um gate width) with no
input matching
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LNA SIMULATIONS
Single stage LNA (800 µm gate width) with
off-chip components.
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LNA SIMULATIONS

• _at_ 1.4 GHz
• NF lt 0.45dB

Single stage LNA (800 µm gate width) with
off-chip components.
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ADC Summary

• AIM Design and fabrication of a 4bit 4GS/s ADC
  consuming 100 mW
• Current state-of-the-art 0.18µm CMOS 4-bit
  4GS/s - 220mW 1

• FULL ADC Results to follow shortly.

1 S. Park, Y. Palaskas, and M. P. Flynn, "A
4GS/s 4b flash ADC in 0.18mm CMOS, IEEE Symp.
On Circuits and Systems, pp 2330 2339, Feb 2006

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ADC Basic Building Blocks
Current work

• Basic Building blocks for the ADC designed using
  ADS
• Coplanar waveguide design
• Differential Amplifier
• Ex-Or/OR/AND
• Latch
• 12-Mask procedure
• HBT (9 masks)
• NiCr Resistors (100 ohms/sq)
• 3 metal layers
• Polyimide dielectric

EX-OR
Complete MMIC
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CONCLUSIONS

• Large periphery transistors are needed for low
  noise resistance Rn and wide band operation
  especially at low frequencies (lt 2GHz).
• A wide range of large periphery multi-finger
  InGaAs/InAlAs pHEMTs have been fabricated (up to
  1.2mm gate width).
• Accurate Linear and Nonlinear models have been
  obtained for these devices.
• Simulated LNA based on this design yield less
  than 0.45dB Noise figure at 1.4GHz even at 1µm
  gate length!
• 4 bit 4GS/s ADC designed, simulated and basic
  building blocks fabricated.
• LNA and ADC are being fabricated now.