EE 365

1
EE 365

• Combinational-Circuit Synthesis

2
Combinational-Circuit Analysis

• Combinational circuits -- outputs depend only on
  current inputs (not on history).
• Kinds of combinational analysis
• exhaustive (truth table)
• algebraic (expressions)
• simulation / test bench
• Write functional description in HDL
• Define test conditions / test vectors, including
  corner cases
• Compare circuit output with functional
  description (or known-good realization)
• Repeat for random test vectors

3
Combinational-Circuit Design

• Sometimes you can write an equation or equations
  directly using logic (the kind in your brain).
• Example (alarm circuit)
• Corresponding circuit

4
Alarm-circuit transformation

• Sum-of-products form
• Useful for programmable logic devices (next lec.)
• Multiply out

5
Sum-of-products form
6
Product-of-sums form
7
Brute-force design
row N3 N2 N1 N0 F 0 0 0 0 0 0
1 0 0 0 1 1 2 0 0 1 0
1 3 0 0 1 1 1 4 0 1 0
0 0 5 0 1 0 1 1 6 0 1
1 0 0 7 0 1 1 1 1 8 1
0 0 0 0 9 1 0 0 1 0 10
1 0 1 0 0 11 0 0 1 1 1 12
1 1 0 0 0 13 1 1 0 1
1 14 1 1 1 0 0 15 1 1 1 1
0

• Truth table --gt canonical sum (sum of minterms)
• Exampleprime-number detector
• 4-bit input, N3N2N1N0

F SN3N2N1N0(1,2,3,5,7,11,13)
8
Minterm list --gt canonical sum
9
Algebraic simplification

• Theorem T8,
• Reduce number of gates and gate inputs

10
Resulting circuit
11
Visualizing T10 -- Karnaugh maps
12
3-variable Karnaugh map
13
Example F S(1,2,5,7)
14
Karnaugh-map usage

• Plot 1s corresponding to minterms of function.
• Circle largest possible rectangular sets of 1s.
• of 1s in set must be power of 2
• OK to cross edges
• Read off product terms, one per circled set.
• Variable is 1 gt include variable
• Variable is 0 gt include complement of variable
• Variable is both 0 and 1 gt variable not
  included
• Circled sets and corresponding product terms are
  called prime implicants
• Minimum number of gates and gate inputs

15
Prime-number detector (again)
16

• When we solved algebraically, we missed one
  simplification -- the circuit below has three
  less gate inputs.

17
Another example
18
Yet another example

• Distinguished 1 cells
• Essential prime implicants

19
Quine-McCluskey algorithm

• This process can be made into a program, using
  appropriate algorithms and data structures.
• Guaranteed to find minimal solution
• Required computation has exponential complexity
  (run time and storage)-- works well for functions
  with up to 8-12 variables, but quickly blows up
  for larger problems.
• Heuristic programs (e.g., Espresso) used for
  larger problems, usually give minimal results.

20
Lots of possibilities

• Can follow a dual procedure to find minimal
  products of sums (OR-AND realization)
• Can modify procedure to handle dont-care input
  combinations.
• Can draw Karnaugh maps with up to six variables.

21
Real-World Logic Design

• Lots more than 6 inputs -- cant use Karnaugh
  maps
• Design correctness more important than gate
  minimization
• Use higher-level language to specify logic
  operations
• Use programs to manipulate logic expressions and
  minimize logic.
• PALASM, ABEL, CUPL -- developed for PLDs
• VHDL, Verilog -- developed for ASICs