On the Feasibility of FewTHz Bipolar Transistors - PowerPoint PPT Presentation

Title: On the Feasibility of FewTHz Bipolar Transistors


1
On the Feasibility of Few-THz Bipolar Transistors
Invited Paper, 2007 IEEE Bipolar Circuits and
Technology Meeting, September 30 - October 3, 2007
M. Rodwell, E. Lind, Z. Griffith, S. R. Bank, A.
M. Crook, U. Singisetti, M. Wistey, G. Burek,
and A. C. GossardUniversity of California, Santa
Barbara
Sponsors J. Zolper, S. Pappert, M. RoskerDARPA
(TFAST, SWIFT, FLARE) D. Purdy, I. MackOffice of
Naval Research Kwok Ng, Jim HutchbySemiconductor
Research Corporation
Now at University of Texas, Austin
Collaborators (HBT) M. Urteaga, R. Pierson , P.
Rowell, M-J Choe, B. BrarTeledyne Scientific
Company X. M. Fang, D. Lubyshev, Y. Wu, J. M.
Fastenau, W.K. Liu International Quantum
Epitaxy, Inc. S. MohneyPenn State University
rodwell_at_ece.ucsb.edu 805-893-3244, 805-893-5705
fax
2
Specific Acknowledgements
(Prof.) Erik Lind 125 nm HBTsprocess
technologytheory / epi design
Dr. Zach Griffith 500 250 nm HBTs150 GHz
Logic100 GHz op-amps
3
THz Transistors are coming soon both InP
Silicon
InP Bipolars 250 nm generation ? 780 GHz fmax ,
424 GHz ft , 4-5 V BVCEO
Z. Griffith
125 nm 62 nm nodes? THz devices
IBM IEDM '06 65 nm SOI CMOS ? 450 GHz fmax , 1
V operation
Intel Jan '07 45 nm / high-K / metal gate
continued rapid progress ? continued pressure
on III-V technologies
If you can't beat them, join them ! unclear
if Si MOSFETs will work well at sub-22-nm gate
length InGaAs/InAs/InP channels under serious
investigation for CMOS VLSI.
Datta, DelAlamo, Sadana, ...
4
THz InP vs. near-THz CMOS different
opportunities
65 / 45 / 33 / 22 ... nm CMOS vast s of very
fast transistors ... having low breakdown,
sloppy DC parameters
what NEW mm-wave applications will this enable
?
DC parameters limit analog precision...
5
THz InP vs. near-THz CMOS different
opportunities
InP HBT THz bandwidths, good breakdown, analog
precision

340 GHz, 70 mW amplifiers (design)In future 700
or 1000 GHz amplifiers ?
M. Jones
200 GHz digital logic (design)In future 450 GHz
clock rate ?
Z. Griffith
30-50 GHz gain-bandwidth op-amps? low IM3 _at_ 2 GHz
In future 200 GHz op-amps for low-IM3 10 GHz
amplifiers?
M. Urteaga (Teledyne)
Z. Griffith
6
Transistor Benchmarks
BVCEO is not the only voltage limit
fmax matters
no gain above 218 GHz
!
Need Safe Operating Area...at least BVceo/2 at
Jmax/2 thermal resistance, high-current
breakdownhigh-temperature operation (75 C) ?
Tuned amplifiers fmax sets bandwidthMixed-signa
l CcbDV/ Ic , CjeDV/ Ic , RexIc/DV
, RbbIc/DV , tf
Goal is gt1 THz ft and fmaxlt50 fs CDV / I
charging delays
? emphasize InP-collector DHBTs
7
HBT Scaling Laws
8
Frequency Limitsand Scaling Laws of (most)
Electron Devices
applies to almost all semiconductor
devicestransistors BJTs HBTs, MOSFETS
HEMTs, Schottky diodes, photodiodes, photo
mixers, RTDs, ...
Applies whenever AC signals are removed though
Ohmic contactsDiode lasers avoid R/C/t limits by
radiating through end facets
9
(No Transcript)
10
InP DHBTs September 2007
250 nm
250 nm
600nm
350 nm
11
HBT Scaling Roadmaps
12
multi-THz InP HBT Scaling Roadmap
emitter 512 256 128 64 32 nm width 16
8 4 2 1 ???m2 access r base 300
175 120 60 30 nm contact width, 20
10 5 2.5 1.25 ???m2 contact r collector 150
106 75 53 37.5 nm thick, 4.5 9 18 36 72
mA/?m2 current density 4.9 4 3.3 2.75 2-2.5
V, breakdown ft 370 520 730 1000 1400
GHz fmax 490 850 1300 2000 2800 GHz power
amplifiers 245 430 660 1000 1400 GHz digital
clock rate 150 240 330 480 660 GHz(static
dividers)
13
HBT Scaling Challenges
14
Scaling challenges What looks easy, what looks
hard ?
HardThermal resistance (particularly
IC-level)Emitter contact access
resistanceBase contact resistanceContact
electromigrationYield in deep submicron processes
high current density, low resistivity contacts,
epitaxial lithographic scaling
THz semiconductor devices
15
Thermal Resistance Scaling Transistor,
Substrate, Package
16
Breakdown Voltage Scaling Expect 2.4 V _at_ 1 THz
ft
mature devices-- full potential ft achieved
newer, immature devices- reduced ft fromhigh
contact parasiticsinsufficient lateral scaling
For mature, well-scaled InP DHBTs, ft x BVCEO
2.4 THz-Volts.
17
HBTs 500 nm Generation
18
512 nm InP DHBT
500 nm mesa HBT
150 GHz M/S latches
175 GHz amplifiers
LaboratoryTechnology
UCSB
UCSB / Teledyne / GCS
DDS IC 4500 HBTs
38 GHz op-amps
500 nm sidewall HBT
Production
( Teledyne )
Teledyne / BAE
Teledyne / UCSB
Teledyne
Z. GriffithM. UrteagaP. RowellD. PiersonB.
BrarV. Paidi
20 GHz clock
46 dBm OIP3 _at_ 2 GHzwith 1 W dissipation
f? 405 GHz fmax 392 GHz Vbr, ceo 4 V
19
HBTs 250 nm Generation
20
256 nm GenerationInP DHBT
150 nm thick collector
70 nm thick collector
340 GHz, 70 mW amplifier design
60 nm thick collector
Z. Griffith, E. Lind, J. Hacker, M. Jones
21
125 nm InP HBTdevelopment
22
125 nm Technology Development
E. Lind
New Emitter Process
First results are at 250 nm emitter width
Simultaneously 560 GHz ft fmax BVceo
3.3V ...can do much better...
Scalable below 128 nm width
23
128 nm InP HBT Technology Development
E. Lind
New Emitter Process for 128 and 64 nm
junctionsdry etched metaldry etched
junctionrefractory W or Mo contact? stable at
very high Jelt 0.8 W-mm2 contact resistivity
New, thin --12 nm -- base-collector grademost
of collector is high-Eg InP? does not degrade
Vbrceo grade sufficiently thin even for 64 nm
HBTs
Je 0mA/mm2, 15mA/mm2, 30mA/mm2
alternative epi layer designs (InP/GaAsSb/InP)
are not necessary
first results close but not perfectslip-ups
wide 250 nm emitters, poor base contactsonly a
560GHz / 560GHz / 3 V devicetarget was 700 / 700
/ 3 ... try again soon...
24
Improvements in Emitter Access Resistance
U. SingisettiA. CrookS. BankE. Lind
125 nm generation requires 5 ? - µm2 emitter
resistivities 65 nm generation requires 1-2 ? -
µm2
Recent Results (ONR contacts program)ErAs/Mb
MBE in-situ 1.5 ? - µm2 Mb MBE in-situ
0.6 ? - µm2 TiPdAu ex-situ 0.5 ? - µm2
TiW ex-situ 0.7 ? - µm2
Degeneracy contributes 1 ? - µm2
20 nm emitter-base depletion layer contributes 1
? - µm2 resistance
Te0 nm
10 nm steps
Te100 nm
25
Current UCSB TiW emitter process
E. Lind
Emitter prior to InP wet etch

• 5 nm Ti layer for improved adhesion
• 25 nm SiNx sidewalls protects Ti/TiW during Cl2
  and BHF etch, improves adhesion
• Standard triple mesa
• BCB passivation

26
RF DC data 70 nm collector, 22 nm base InP
Type-I DHBT
E. Lind
Emitter width 250 nm First reported device with
ft, fmax gt 500 GHz BVCEO 3.3 V, BVCBO 3.9 V
(Je,c 15kA/cm2) Emitter contact (from RF
extraction), Rcont lt 5 ???m2 Base Rsheet 780
?/sq, Rcont 15 ???m2 Collector Rsheet 11.1
?/sq, Rcont 10.1 ???m2
27
64 nm 32 nm (THz) InP HBT
28
64 32 nm Generations Example Process Flow
One critical lithographic step, no critical
alignments Refractory base and emitter
contacts Base-emitter ledge for leakage current
control
29
Reliability...
...depends upon stress and upon device
structure.
high current density? heatingthermal design is
critical
high current density? contact electromigrationnee
d refractory (W, TiW, Mo,...) contacts
must investigate failure mechanismsdriven by
high current density in semiconductor dark-line
defects
Given the need for large I/C charging rates,
high current density is unavoidable.
30
Interconnects Substrate Microstrip Has Problems
Zero ground inductance in package
Thick Substrate ? low skin loss
No ground planebreaks in IC
High via inductance
TM substrate mode coupling
Strong coupling when substrate approaches ld / 4
thickness
12 pH for 100 mm substrate -- 7.5 W _at_ 100 GHz
lines must be widely spaced
ground vias must be widely spaced
all factors require very thin substrates for gt100
GHz ICs? lapping to 50 mm substrate thickness
typical for 100 GHz
Line spacings must be 3(substrate thickness)
31
Interconnect Coplanar Waveguide Has Many
Problems !
No ground viasNo need (???) to thin substrate
Hard to ground IC to package
ground plane breaks ? loss of ground integrity
III-Vsemi-insulating substrate? substrate mode
coupling ? must thin wafer to ld/2 , must have
vias to kill microstrip mode. Siliconconducting
substrate? substrate conductivity losses
substrate mode coupling or substrate losses
? substrate must be thinned !
Repairing ground plane with ground straps is
effective only in simple ICsIn more complex CPW
ICs, ground plane rapidly vanishes ? common-lead
inductance ? strong circuit-circuit coupling
poor ground integrity
loss of impedance control
ground bounce
coupling, EMI, oscillation
40 Gb/s differential TWA modulator drivernote
CPW lines, fragmented ground plane
35 GHz master-slave latch in CPWnote fragmented
ground plane
175 GHz tuned amplifier in CPWnote fragmented
ground plane
32
THz IC Interconnects will be Silicon-Like
Microstrip wiring metal 4 ground planeP-doped
substrate, junction isolation? kill substrate
modes, negligible substrate capacitanceThrough-wa
fer thermal vias (etch stop) ? address device
IC thermal scalingThrough-wafer electrical vias
(no etch stop) ? low-ground-bounce IC-package
connection
33
Comparison to SiGe
34
SiGe Today Parasitic Reduction for Increased
Bandwidth
wide emitter contact low resistance narrow
emitter junction scaling (low Rbb/Ae)
thick extrinsic base low resistance thin
intrinsic base low transit time
wide base contacts low resistancenarrow
collector junction low capacitance
These are planar approximations toradial
contacts
extrinsic emitter
extrinsic base
extrinsic base
N subcollector
? reduced access resistance
35
Parasitic Reduction Could Help Less with Small
Devices
Scaling for increased HBT bandwidth Lateral
dimensions vary as (bandwidth)-1 , vertical as
(bandwidth)-2. ? Proportionally larger parasitic
capacitances from extrinsic contact regions.
Let us compare intrinsic device structures...
36
InP vs. SiGe Comparison with Intrinsic Device
Assumption Mesa structure, change from SiGe to
InP, keep the same bandwidth
? about 3.51 larger dimensions, 3.51 larger
breakdown for a given device bandwidth
? higher bandwidths achieved due to high
velocities and low resistance contacts
37
On the Feasibility of Few-THz Bipolar Transistors
InP Bipolar Transistors
Scaling limits contact resistivities, device and
IC thermal resistances.
62 nm (1 THz ft , 1.5 THz fmax ) scaling
generation is feasible.
700 GHz amplifiers, 450 GHz digital logic
Is the 32 nm (1 THz amplifiers) generation
feasible ?
SiGe Bipolar Transistors Sophisticated device
structure ? harder to project further
progress Contact access resistivies thermal
resistivities are key scaling limits
38
(end)
39
non-animated versions of the three key scaling
slides
40
HBT scaling laws
Goal double transistor bandwidth when used in
any circuit ? keep constant all resistances,
voltages, currents ? reduce 21 all
capacitances and all transport delays
? thin base 1.4141
? thin collector 21
? reduce junction areas 41
? reduce emitter contact resistivity 41
(current remains constant, as desired )
need to reduce junction areas 41reduce widths
21 reduce length 21 ? doubles DTreducing
widths 41, keep constant length? small DT
increase
?
? reduce base contact resistivity 41
?
reduce widths 21 reduce length 21 ? constant
Rbb reducing widths 41, keep constant length ?
reduced Rbb
??
Linewidths scale as the inverse square of
bandwidth because thermal constraints dominate.
41
First-Order HBT Design