Lab 2 4-Bit Adder

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Lab 24-Bit Adder

• Digilent Spartan 3 Board
• Lecture L2.3

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4-Bit Adder
component adder4 port( A in
std_logic_vector(3 downto 0) B in
std_logic_vector(3 downto 0) carry out
std_logic S out std_logic_vector(3 downto
0)) end component
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Top-level Design
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library IEEE use IEEE.STD_LOGIC_1164.all use
IEEE.std_logic_unsigned.all entity Lab2 is
port( mclk in STD_LOGIC SW in
STD_LOGIC_VECTOR(7 downto 0) BTN in
STD_LOGIC_VECTOR(3 downto 0) LD out
STD_LOGIC_VECTOR(7 downto 0) AtoG out
STD_LOGIC_VECTOR(6 downto 0) dp out
STD_LOGIC AN out STD_LOGIC_VECTOR(3 downto
0) ) end Lab2
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x7seg
component x7seg port( x in
std_logic_vector(15 downto 0) cclk in
std_logic clr in std_logic AtoG out
std_logic_vector(6 downto 0) AN out
std_logic_vector(3 downto 0)) end component
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Clock Divider
signal cclk, carry std_logic signal clkdiv
std_logic_vector(23 downto 0) begin --
Divide the master clock (50Mhz) down to a lower
frequency. process (mclk) begin if mclk
'1' and mclk'Event then clkdiv lt clkdiv
1 end if end process cclk lt
clkdiv(17) -- 381 Hz 50000000 / 217
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signal ground std_logic_vector(2 downto
0) signal sum std_logic_vector(3 downto
0) begin ground lt "000" dp lt
'1' U1 adder4 port map (A gt SW(7 downto
4), B gt SW(3 downto 0), S gt sum, carry gt
carry) U2 x7seg port map (x(15 downto
12) gt SW(7 downto 4), x(11 downto 8) gt SW(3
downto 0), x(7 downto 4) gt sum, x(3 downto 1)
gt ground, x(0) gt carry, clr gt BTN(3), cclk gt
cclk, AN gt AN, AtoG gt AtoG) LD(7
downto 4) lt BTN LD(3 downto 0) lt BTN
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signal ground std_logic_vector(2 downto
0) signal sum std_logic_vector(3 downto
0) begin ground lt "000" dp lt '1'
U1 adder4 port map (A gt SW(7 downto 4), B
gt SW(3 downto 0), S gt sum, carry gt carry)
U2 x7seg port map (x(15 downto 12) gt SW(7
downto 4), x(11 downto 8) gt SW(3 downto 0),
x(7 downto 4) gt sum, x(3 downto 1) gt ground,
x(0) gt carry, clr gt BTN(3), cclk gt cclk, AN
gt AN, AtoG gt AtoG) LD(7 downto 4) lt
BTN LD(3 downto 0) lt BTN
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signal ground std_logic_vector(2 downto
0) signal sum std_logic_vector(3 downto
0) begin ground lt "000" dp lt
'1' U1 adder4 port map (A gt SW(7 downto
4), B gt SW(3 downto 0), S gt sum, carry gt
carry) U2 x7seg port map (x(15 downto
12) gt SW(7 downto 4), x(11 downto 8) gt SW(3
downto 0), x(7 downto 4) gt sum, x(3 downto 1)
gt ground, x(0) gt carry, clr gt BTN(3), cclk gt
cclk, AN gt AN, AtoG gt AtoG) LD(7
downto 4) lt BTN LD(3 downto 0) lt BTN
10
signal ground std_logic_vector(2 downto
0) signal sum std_logic_vector(3 downto
0) begin ground lt "000" dp lt
'1' U1 adder4 port map (A gt SW(7 downto
4), B gt SW(3 downto 0), S gt sum, carry gt
carry) U2 x7seg port map (x(15 downto
12) gt SW(7 downto 4), x(11 downto 8) gt SW(3
downto 0), x(7 downto 4) gt sum, x(3 downto 1)
gt ground, x(0) gt carry, clr gt BTN(3), cclk gt
cclk, AN gt AN, AtoG gt AtoG) LD(7
downto 4) lt BTN LD(3 downto 0) lt BTN