Design of 4-bit ALU Motorola SN54/74LS181

1
Design of 4-bit ALUMotorola SN54/74LS181

• Madhurima Kondepudi
• Suma Marepally
• Vani Venkatrao
• Vidya Devarasetty
• Advisor Dr. David W. Parent
• 11th May 2005

2
Agenda

• Abstract
• Introduction
• Why
• Simple Theory
• Back Ground information (Lit Review)
• Summary of Results
• Project (Experimental) Details
• Results
• Cost Analysis
• Conclusions

3
Abstract

• Goal is to design a 4-bit ALU driving a load of
  30fF in 5ns.
• Perform 16 Arithmetic operations.
• Perform 16 Logical operations.
• The data should be transferred at clock rates of
  200 MHz, with .6ns setup and hold times.
• Maximum power is 50mW.
• Maximum area is 500x500µm2

4
Introduction

• Why this project?
• The Arithmetic and logic Unit is a building
  block of several circuits.
• Challenging to design a 16 logic level design
  working at 5ns.
• Design consists of different kinds of logic
  Ripple Carry Adder, Subtractor, Transfer Data,
  DFF, Decoders, Inv, Nand, Nor, Xor, etc.

5
ALU Block Diagram
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Function Table
A, B 4 Bit Input, M , S0, S1 Status Control
Pin Cn Carry in
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Project Summary

• The ALU performs 16 Arithmetic functions and 16
  Logical functions at 200MHz.
• Uses Ripple carry adder to perform addition.
• Design uses maximum power of 18.9mW
• Maximum area is 403 x 335µm2

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Design Flow
9
Longest Path
 
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Longest Path Calculations
CELL Cint Cg tphl NSN NSP N M R WN WP
  F F s cm cm
INV 2.00E-14 3.0000E-14 1.00E-10 1 1 1 1 1.805 5.44E-04 9.81E-04
NOR 2.00E-14 5.1173E-14 1.90E-10 1 2 2 3 2.000 4.96E-04 9.91E-04
NAND 2.00E-14 4.9907E-14 2.20E-10 2 1 3 2 1.000 8.73E-04 8.73E-04
XNOR 2.00E-14 5.8595E-14 4.50E-10 2 2 4 6 1.718 5.81E-04 9.98E-04
INV 2.00E-14 2.6487E-14 1.00E-10 1 1 1 1 1.805 5.07E-04 9.15E-04
NAND 2.00E-14 4.7736E-14 2.20E-10 2 1 3 2 1.000 8.48E-04 8.48E-04
NOR 2.00E-14 5.6913E-14 2.00E-10 1 2 2 3 2.000 4.85E-04 9.70E-04
NOR 2.00E-14 4.8831E-14 1.90E-10 1 2 2 3 2.000 4.81E-04 9.61E-04
NAND 2.00E-14 4.8388E-14 2.20E-10 2 1 3 2 1.000 8.55E-04 8.55E-04
NOR 2.00E-14 8.6127E-14 4.00E-10 1 2 2 3 2.000 4.31E-04 8.63E-04
INV 2.00E-14 2.1723E-14 1.00E-10 1 1 1 1 1.805 4.58E-04 8.26E-04
NAND 2.00E-14 6.4611E-14 2.50E-10 2 1 3 2 1.000 8.19E-04 8.19E-04
INV 2.00E-14 2.7483E-14 1.10E-10 1 1 1 1 1.803 4.51E-04 8.13E-04
INV 2.00E-14 2.1205E-14 1.10E-10 1 1 1 1 1.803 3.94E-04 7.10E-04
Total Propagation delay for the longest path
2.86ns
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Gate Level Diagram
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Schematic - Top Level
Schematic- Top-Level
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Simulation-1(Logical Operations)
F (AB) '
F A'
F (A'B)
F Logical 1
S4, M1, (AB)
F (A XOR B) '
F (AB) '
F AB'
F B'
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Simulation-2 (Arithmetic Operations)
F AB - 1
F AB'- 1
F minus 1
F A - 1
F A plus (AB)
F A plusB
F AB plus(AB')
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Layout
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Verification
DRC Results
NETLISTS MATCH
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Transient Response
A0, B1, M0, SE, F0 F1F2 F3 0, F AB
plus A
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Transient Response -Power
Total Power 18.9mW
19
Results

• The ALU performs all 32 functions at a 200MHz
  clock and a load of 30fF.
• Power dissipation is 18.9mW.
• Area of the layout is 403 x 335µm2

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Cost Analysis

• Time spent on each phase of the project
• Logic check 1 week.
• Gate level design 2 weeks.
• Integration of schematic blocks and verification
  2weeks.
• Layout 2 weeks.
• Post extraction check 3 days.

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Conclusions

• Designed and tested almost all the design units
  that we learnt in the class.
• Designed a 4-Bit ALU that performs sixteen
  arithmetic and sixteen logical functions at
  200MHz frequency with setup and hold time 0.6ns,
  driving up to 30fF.
• This circuit can be used as a building block for
  16/32-bit ALU.
• The Logic design can be modified to perform more
  functions.

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Lessons Learned

• Uniform cell height.
• No bends in the poly.
• Learned to fix LVS errors using extracted view.

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Acknowledgements

• Thanks to Cadence Design Systems for the VLSI lab
• Thanks to Professor David W. Parent for his
  guidance.