Dynamic Power Noise Analysis Method for Memory Designs

1
Dynamic Power Noise Analysis Method for Memory
Designs

• Chanseok Hwang, Changwoo Kang, Bosun Hwang Joonho
  Choi, Moonhyun Yoo
• CAE Team, Semiconductor Research Center Samsung
  Electronics

2
Outline

• Memory Design Overview
• Memory Core Operations
• Our approach
• Memory Core Circuit Modeling
• Power Grid Creation and Reduction
• Simulation Results
• Conclusions

3
Memory Design Overview

• Power noise increasingly affects circuit
  robustness
• Low VDD (lt 1.0V), High Speed (gt2GHz)
• Challenges in power noise analysis
• Modeling of huge power network
• Long simulation times

An Example of DRAM Fullchip Power Grid
4
DRAM Core Operations

• Core AC parameters Sensing/Restore Time
• Highly sensitive to power noises Voltage margin
  and Operation speed

VDD
VCELL
VCELL 1.125(90 VDD)
LAB
VBL
WL
VBL500mv
BL
LAB
BLB
Sensing time
VSS
LA
Restore time
Sense amplifiers with power networks
Simulation waveforms of sensing operation
5
Our Approach

• Current Source Model (CSM)
• Core sub-array block is replaced by a current
  source
• Multi-banks operation can be simulated
• Power Network Generation Reduction
• Memory core power network is generated
  automatically
• MOR technique is adopted efficiently

6
Current Source Modeling
7
Multiple-Bank Operations
Activate Bank H
Activate Bank F
A
C
E
G
A
C
E
G
7ns
B
D
F
H
B
D
F
H
Activate Bank B, C, F, G
Activate Bank A, D, E, H
A
C
E
G
10ns
B
D
F
H
current sources
circuits
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Our Approach

• Current Source Model (CSM)
• Core sub-array block is replaced by a current
  source
• Multiple-Bank Operation Modeling
• Power Network Generation Reduction
• Memory core power network is generated
  automatically in early design stages
• MOR technique is adopted efficiently

9
Power Network Generation Reduction
Automatically Generated Power Network
amp
amp
amp
amp
pad
amp
amp
amp
amp
amp
amp
Power Network Generation GUI
Reduced Power Network
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Power Noise Verification Flow
Active Circuits
Current Sources

Power Network Creation
Simulation Waveform
Circuit connection to power network
Circuit Simulation
Voltage Drop Map Viewer
Verification
Fail
11
Simulation Results

• Example Circuit 1G DRAM
• Sensing Restore Time Comparisons
• Simulation Time and Accuracy for the Proposed
  Power Network Model
• Single Bank vs. Multiple Bank Operations

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Results Analysis of different power networks
Original Power Network Modeling (OPN) Proposed Power Network Modeling (CSM) Rate (OPN/CSM)
Num. Resistor 2,316,868 493,943 4.69
Num. Capacitor 1,307,124 66,515 19.65
Run time (h) 35.3 2.3 15.35
Sensing time (ns) 1.059 1.053 1.01
Restore time (ns) 11.643 12.625 0.92

• Run-Time 15.3X reduction
• Accuracy Error 1 in Sensing, 8 in Restore time

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Simulation Results

• We could get this results by using the proposed
  method.

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Conclusions

• Current Source-based Model is proposed for the
  power noise analysis of memory circuits.
• Based on the hierarchical memory core array
  structure
• The method of automatic generation and reduction
  of power networks at design early stage is
  suggested.
• In Simulation Results 1G DRAM
• Simulation time reduction gt 15X
• Analysis error lt 8
• Due to the reduced complexity the simulation of
  multiple-bank operations was possible.

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Thank You!