Analytical Static Noise Margin characterization for SOI Ultra-Low-Voltage memory cell

1
Analytical Static Noise Margin characterization
for SOI Ultra-Low-Voltage memory cell
FTFC2003

• Olivier THOMAS
• Amara AMARA
• Andrei VLADIMIRESCU

2
Outline

• Motivations
• Static noise disturbance
• Static noise margin (SNM) characterization
• Electrical analytic model
• Analytic estimation method of the stability
• Stability analysis on a 4T Self-Refresh and a 6T
  full CMOS SRAM cell
• Conclusions

3
Motivations

• The emergence of portable or mobile computing and
  communication devices is the most important
  factor driving the need for low power design.
• The commercial success of such a product depends
  on the battery life.
• Some niche applications do not necessarily need
  high performance.
• ? Operation in Ultra-Low-Voltage is very
  attractive for achieving significant energy
  saving.

4
Outline

• Motivations
• Static noise disturbance
• Static noise margin (SNM) characterization
• Electrical analytic model
• Analytic estimation method of the stability
• Stability analysis on a 4T Self-Refresh and a 6T
  full CMOS SRAM cell
• Conclusions

5
Static noise disturbance presents in logic gates

• Cell stability is influenced by offsets and
  mismatches due to processing and variations in
  operating conditions
• Width and length mismatches
• Threshold mismatches (non-uniformity of ion
  implantation or gate oxide thickness)
• Also there are 4 other basic types of noise
  sources
• Series-voltage noise in interconnection lines
  between gates
• induced by inductive coupling to a current
  gradient di/dt
• Charge coupling to inputs or outputs gates
• introduced by capacitive coupling to a voltage
  gradient dV/dt
• Ground and power-supply lines voltage noise
• caused by ringing, spikes, voltage drops due to
  series resistances, etc.

Considered as quasi-static if the interval time
in which the gradient is present is long compared
with the switching speed of the inverting gates
6
SOI Transistors disturbance
Good isolation between devices
Less junction capacitance
DTMOS (Dynamic Threshold MOS)
Body Tied to Source
7
SOI DC characterization in Ultra-Low-Voltage

• In U-L-V (VDD? VTH)
• Iii ltlt due to a weak E _at_ drain

8
SOI TRAN characterization in Ultra-Low-Voltage

• VDD close to VT ? The threshold voltage strongly
  depends on the coupling capacitance CG-B and
  CD/S-B.
• Voltage transfer characteristic of an Invertor
• I.C.
• --- VIN 1?0
• --- VIN 0?1
• Charge coupling to body

9
Outline

• Motivations
• Static noise disturbance
• Static noise margin (SNM) characterization
• Electrical analytic model
• Analytic estimation method of the stability
• Stability analysis on a 4T Self-Refresh and a 6T
  full CMOS SRAM cell
• Conclusions

10
Static Noise Margin (SNM) characterization

• The SNM of a SRAM memory cell is defined as the
  minimum DC noise voltage (Vn) present at each of
  the cell storage nodes (A and B) necessary to
  flip the state of the cell to a wrong state.
• The memory cell is more vulnerable during a read
  access.

11
SNM characterization criteria overview

• Maximum Square between normal and mirrored
  voltage transfer characteristic.
• Small-Signal Closed-Loop Gain is Unity.
• Jacobian of the Kirchhoff equations is Zero.
• Coincidence of Roots of the flip-flop equation.
• All of these criteria are equivalent
• The SRAM cell stability studies usually is based
  on the Maximum Square method
• J. LOHSTROH, E. SEEVINCK

12
Maximum square method

• The SNM is obtained by drawing and mirroring the
  inverter characteristics and finding the maximum
  possible square between them.
• The SNM value results as the smallest edge value
  of the two squares.

13
Outline

• Motivations
• Static noise disturbance
• Static noise margin (SNM) characterization
• Electrical analytic model
• Analytic estimation method of the stability
• Stability analysis on a 4T Self-Refresh and a 6T
  full CMOS SRAM cell
• Conclusions

14
Subthreshold analytical model used

• ISEP, ESSCIRC SEP 02

15
VBS for floating-body transistor

• The equation was derived by curve fitting
• m1 and m2 are stored in a lookup table for
  different transistor W.
• m is a fitting constant
• The dependence of VBS on VGS in DC is not
  significant
• The resulting error is around 3.5 when m1 and m2
  are extrapolated at VGS equal VDD/2

16
Outline

• Motivations
• Static noise disturbance
• Static noise margin (SNM) characterization
• Electrical analytic model
• Analytic estimation method of the stability
• Stability analysis on a 4T Self-Refresh and a 6T
  full CMOS SRAM cell
• Conclusions

17
Analytic estimation method of the stability

• The SNM estimator has been developed with MATLAB
• Methodology
• In retention mode, the floating body potential of
  each transistor of the memory cell is computed
  analytically.
• In read mode, the VTC for each half cell is
  derived taking into account the body potential
  previously computed. In addition body voltage
  variation induced by gate-body coupling is added.
• Finally the SNM is extracted graphically by
  considering the maximum possible square between
  the normal and mirrored transfer characteristic.

18
Outline

• Motivations
• Static noise disturbance
• Static noise margin (SNM) characterization
• Electrical analytic model
• Analytic estimation method of the stability
• Stability analysis on a 4T Self-Refresh and a 6T
  full CMOS SRAM cell
• Conclusions

19
Simulation environment

• Technology SOI 0.25µm
• VT0N,P close to 0.6v
• 0.5 ? Wp/Wn ? 0.7 _at_ VDSVDD ?(VBS)
• Simulation condition VDD 0.4v

20
4T Self-Refresh SRAM cell

• Designed for Ultra-Low-Voltage
• 4T S-R architecture
• 2 FB NMOS access transistors
• 2 pDTMOS load transistors
• Low leakage current
• High drive current

21
Stability in retention mode

• BLT BLC grounded to VSS
• WL maintained at 0V
• TL1 is ON
• TA1, TA2 TL2 are OFF
• Easy to maintain 1
• IonL1 gtgt IoffA1
• Level 0 depends on IA2 IL2
• IoffA2(VBS,VDS) IoffL2(VDS)
• If V(0) ? ? VBS(TA2), VDS(TA2) ? and VDS(TL2)
  ?
• IoffA2 goes exponentialy up and IoffA2 becomes
  higher than IoffL2
• Self refresh behavior

22
Stability versus qWA/WL

• Stability depends on the ratio
• The error between the estimated and the simulated
  curves is less than 3 for a ratio q larger than
  1.5
• The higher the ratio q, the better the stability

23
Stability in read mode

• VTC without considering the gate-body coupling
• Good fit between simulated and analytical results

• VTC with and without considering the gate-body
  coupling
• VTCs are degraded

• The SNM is affected deeply by the gate-body
  coupling
• For 250mV variation the SNM is divided by 2
• The higher the ratio q, worse the stability

This study shows that the ratio q must be
well-balanced versus retention and read mode
results
24
6T Full CMOS SRAM cell

• In retention mode
• BLT BLC grounded to VSS
• WL maintained at 0V
• VTCT and VTCC are not symmetrical
• In retention
• VSTA2 0v ? VBTA2 lt 0v ( -74mV)
• VSTA1 VDD ? VBTA1 gt 0v ( 315mV)
• In read mode VBS of TA2 becomes more and more
  negative as V(B) increases, which preventing the
  voltage to reach VDD.

25
Stability in read mode

• VTC with and without considering the gate-body
  coupling
• VTCs are degraded

26
Outline

• Motivations
• Static noise disturbance
• Static noise margin (SNM) characterization
• Electrical analytic model
• Analytic estimation method of the stability
• Stability analysis on a 4T Self-Refresh and a 6T
  full CMOS SRAM cell
• Conclusions

27
Conclusions

• We have developed a simple analytical method to
  evaluated the SNM of SRAM SOI memory cell working
  in subthreshold.
• This analytical method is based on a simple
  analytical subthreshold estimation model.
• This study shows the importance of the floating
  body potential when analyzing the stability of
  CMOS SOI memory cells.
• Gate-to-body coupling for the access transistors
  adds a new important constraint on the stability
  when the word-line is activated.
• For stability reasons the 6T floating-body memory
  cell working in subthreshold requires small
  ratios qWA/WL and rWA/WD.
• For the 4T S-R cell a good stability is reached
  for a high ratio qWA/WL.