PRR QA/QC

1
Detector DAQ Status
Jean-Sebastien Graulich, Geneva

• Since CM16
• Detector DAQ software
• Front End Electronics
• Schedule Milestones
• Summary

2
Since CM16

• DAQ Software Training in CERN-ALICE group
  Completed
• We have been officially granted the right to use
  DATE
• Test of Front End Electronics for TOF and EMCal
• Decision to use CAEN V1724, 100 MHz, 14 bit flash
  ADC
• Successful tests of the Shaper/Amplifier coupled
  to the flash ADC
• Decision to use Lecroy 4415A Discriminators
  available in Geneva for TOF in Phase 1.
• Start working on a technical design for the
  Particle Trigger

3
DATE Vocabulary

• LDC Local Data Concentrator
• The PC connected to the VME crate via the PC-VME
  Interface
• GDC Global Data Collector
• Event Builder
• Event
• DATE Event DAQ Event !!! It contains data for
  several Particle Events (600)
• Trigger Receiver
• Input Register (with several inputs) receiving
  the signal informing the LDCs that something has
  happened, e.g the spill is finished and the data
  should be readout ( DAQ Trigger)
• Event Type
• Tag attached to the event depending on which
  trigger receivers input has been used.

4
DATE Readout Process

• Two processes running in each LDC
• The readout process waits for a trigger, reads
  out the front-end electronics, and fills a FIFO
  buffer with the sub-event data
• The recorder process off-loads the FIFO and sends
  the sub-event data to one (or several) GDC over
  the network
• Each LDC contains a set of Equipments
• Equipment 1 Vme board (in MICE)
• Each equipment has its own set of routines for
  its initialization and readout.
• Adding an equipment is done without recompiling
  all DATE
• Equipment configuration data is saved in MYSQL
  database (but not archived)

5
DATE Readout Algorithm

• General algorithm for equipment readout

• 5 user routines have to be implemented
• (XXX is the name of the equipment)
• ArmHwXXX
• Executed at the beginning of the Run
• Allows initialization of the board
• AsynchReadXXX
• Executed constantly even when there is no trigger
• Dont use !
• EventArrivedXXX
• Used only if the equipment needs to trigger the
  readout ( Trigger Receiver)
• ReadEventXXX
• That is the readout itself
• DisArmHwXXX
• Executed at the end of the Run

6
DATE Data Format

• The data sent by the equipment is just wrapped
  with a LDC header ( a GDC header if used)
• The data format in the payload is defined by the
  manufacturer of the equipment ! (we will stick to
  32 bits words)
• DATE Header format defined in a header file
  event.h
• This file contains all the information the
  offline codes needs to know about DATE

• Data from the equipment -gt

7
FEE Tests with cosmics

• Testing the CAEN V1724, 14 bits, 100 MHz Flash
  ADC
• Test similar to the one presented at CM16 for the
  SIS3320
• Improvement each PMT now connected to a TDC a
  QDC and a FADC

TDC
Shaper
QDC
Discr.
FADC
Trigger Counter
FADC
Shaper
QDC
Discr.
TDC
Test done with TOF Scintillator bar and EMCal
Pmts EMCal Twisted pair Cable gt new shaper
prototype
8
Shaper Output
Need for better tuning of baseline restorer
Used for individual baseline evaluation
Time (sample)
The signal shape is still very well understood
9
Charge and Time from FADC

• The amplitude of the shaped signal is
  proportional to the original charge
• Very simple algorithm gt Save CPU for offline
  analysis
• Comparing MAX with INTEGRAL allows simple
  detection of pile up
• In case of pile up gt Need more sophisticate
  algorithm

Voltage (adc ch)
Max Q
30 Max
25
50
30
40
35
45
T_th
Time (sample)
10
Charge Resolution
Double peak caused by 50 Hz structured noise on
the base line (observed on the scope, also on
the QDC line)
11
Charge Resolution

• Very good linearity
• The few points off the line are
• Out of QDC gate signal
• Noise in the line
• Pile up (rare)
• Intrinsic Resolution of FADC 1.8 QDC channels
  equivalent
• Better than the QDC itself 2.4 QDC channels

12
Time Resolution

• Looking at the Time difference between Left and
  Right Pmts
• TDC is sensitive to Time Walk (and to the track
  angle)
• gt Applying cuts on charge deposit in both PMTs
  makes the tail disappear

13
Time Correlation
4 cm wide trigger counter
Sigma 490 ps
Time Difference in FADC (ns)
Sigma 455 ps
Slope 1
Time Difference in TDC (ns)

• Resolution for time measurement in FADC 210 ps
• Starting from 10 ns Sampling Period !
• Assuming 100 ps resolution for the TDC
  measurement (including residual time walk)

14
Linearity

• Trigger counter moved by and - 10 cm
• Peak shift TDC not linear / FADC linear
• Refraction Index TDCn 2.2 / FADCn 1.41
• Sigma Not constant / Constant
• Time difference in TDC is sensitive to Time Walk
• Moving the trigger detector changes the relative
  amplitudes in Left and Right PMTs

15
Shaper design
See Roumens talk

• 2 stages vs 4 stages

Same Charge resolution The 4 stages has more
noise But also more gain

• Output is more symmetrical with 4 stages
• Components can be adjusted to reduce the full
  width while keeping the rise time gt 4 samples
• The aim is to keep the width lt 450 ps so that we
  can record 10 samples before the signal (for the
  baseline measurement) and miss only one beam
  burst
• It allows reducing the occupancy time
• gt Reducing the level of segmentation in SW (less
  channels -gt less )

16
PID FEE for Stage 1

• Summary

FADC V1724 Shaper TDC V1290 Discri LS 4415A
TOF 0 40 40 40 40
TOF1 28 28 28 28
TOF2 40? 40? 40? 40?
CKOV 8 8 - -
KL 42 42 - -
SW ?? ?? - -
TOTAL 158 ( SW) 20 boards 158 ( SW) 10 boards 108 3 boards 12 ch 108 7 boards
17
FEE for Stage 1

• We have already 10 LS 4415A in hand
• Ludovico has ordered 18 FADCs and 2 TDCs
• Maurizio has ordered 1 TDC
• Shaper production should start soon
• We should be ready to start with EMCal(KL) /
  TOF0 / TOF1 / CKOV
• For TOF2, we miss
• 2 FADCs
• 1 TDC (actually, only 12 channels)
• For EMCal(SW), we miss even the number of
  channels
• The commercial agreement with CAEN is to buy 30
  FADCs -gt Min 80 ch
• Original EMCal Design 240 channels in total -gt
  Max 200 ch

18
Particle Trigger Technical Design

• Work in Progress
• The current plan is to use Lecroy Logic Unit 4516
  (CAMAC)
• 2 in hand, 3 needed (one per TOF station)
• 9 available in CERNs pool, (8 CHF/month, only
  reduced support)
• VME CAMAC interface available for programming
  the logic (trivial programming)
• CAMAC crates available in Geneva
• Time reference for the trigger is the Burst Gate
• Present in all trigger condition -gt Time
  reference wont change (same offline cuts)
• Discussion ongoing on the availability of the
  Burst Gate..

19
Dispatch Panel (in Hand)
These 4 channels Going to another splitter
20
LEFT Pmts
OR of 10 slabs
UP and DOWN Pmts are not used for the trigger
2 by 2 coincidence
RIGHT Pmts
21
Schedule Milestones

• Complete Flash ADC analysis Nov 2006
• Actually assed in beginning of December
• BUT extended to test new shaper prototype with
  EMCal Pmts -gt Feb 2007
• DAQ Test bench including Event builder Feb 2007
• Delayed by 1 month
• Order Hardware for Stage 1 March 2007
• Critical item Network Switches should be ordered
  at the end of March
• Shaper production process will be launched
• Event builder will be ordered in April
• Move DDAQ system to RAL July 2007
• Still reachable

22
Summary

• DATE software training Completed
• FE Electronics for PID has converged to a valid
  solution achievable for Stage 1
• DAQ test bench is late
• Particle Trigger technical design progressing
• We still plan to install the DAQ system at RAL in
  July