USB 2.0 Host Controller Specification

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(No Transcript)
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USB 2.0 Host ControllerSpecification Compliance

• John S. Howard
• Intel Corporation

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Agenda

• EHCI Development Overview
• EHCI Architecture/Key Features
• USB 2.0 Host Controller Architecture
• EHCI HC Interface Architecture
• Updates for revision 0.96
• USB2 Host Controller Compliance Program
• Summary

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Development Overview

• Enhanced Host Controller Specification for USB
• Defines the architecture for a USB 2.0 capable
  host controller, and
• Defines register (hardware/software)
  interfacefor a high-speed capable host
  controller
• Revisions
• Current 0.95 (11/2000)
• 1.0 planned to be available first half of 2002

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Development Overview
Continued

• Intel developed specification w/contributions
• NEC, Lucent (Agere), Philips, HP, Compaq and
  Microsoft
• Licensees can also suggest contributes to
  specification
• License agreement with Intel
• Pre-1.0 specification revision(s), the license
  agreement provides reciprocal royalty free
  license to manufacture compliant discrete USB 2.0
  host controllers
• 1.0 specification revision, the license agreement
  provides reciprocal royalty free license to
  manufacture compliant USB 2.0 host controllers.
  This includes discrete and integrated
  implementations

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Development Overview
Goals Requirements

• Evolutionary approach
• Use best features from USB 1.1 Controllers
• Mix of OHCI and UHCI
• Re-use existing technology where possible
• Learn from USB 1.1 Controller issues
• Maintain maximum device support and control
• Support 32 64-bit addressing
• Support PCI Power Management

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Agenda

• EHCI Development Overview
• EHCI Architecture/Key Features
• USB 2.0 Host Controller Architecture
• EHCI HC Interface Architecture
• Updates for revision 0.96
• USB2 Host Controller Compliance Program
• Summary

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USB 2.0 Host Controller Architecture
USB 2.0 Host Controller (HC)
High-Speed (Enhanced Interface) USB HC
Companion USB HCs for FS/LS
HC Control Logic/DataBuffering
Enhanced HC Control Logic Enhanced Data Buffering
Port 1
Port 1
Port 2
Port N
Port 2
Port N
Port Owner Control(s)
Port Routing Logic
Port 1
Port 2
Port N

• Benefits
• Companion Controller(s) support FS/LS devices on
  root ports
• High-speed Host Controller support HS devices on
  root ports
• Simpler design optimized for high-speed
  functionality
• Reuses USB 1.1 Host Controller Designs (drop-in)
• USB ports work independent of high-speed capable
  software

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EHCI Interface Architecture
Memory-BasedI/O Registers
PCI ConfigurationRegister
Shared Memory Work Schedules
CapabilityRegisters
PCI ClassCode, etc.
OperationalRegisters
USB Base Address
Periodic Schedule
Asynchronous Schedule
PCI PowerManagementInterface
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EHCI Interface
I/O Space

• EHCI Capabilities
• Optional Feature Indicators and Parameters
• Structural Parameters
• Operational Space
• Command/Configuration
• Host Controller Status
• Interrupt Enables
• Schedule Base References
• Periodic Schedule
• Asynchronous Schedule
• USB Hub Port Status and Control

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EHCI Interface
Data Structures

• Small set of data structures support transfers to
• All transfer types
• All device speeds, including split transactions
• 32-bit and 64-bit addressing support
• Transfer-oriented ( Bulk/Control/Interrupt )
• Large buffer per data structure
• Queue semantics
• Packet-oriented ( Isochronous )
• Frame (millisecond) based
• Exposes per micro-frame programmability
• Simple hardware support for Scatter/Gather onall
  data structures

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EHCI Work Schedules
Shared Memory Work Schedules

• One Periodic Schedule
• Maintains all Isochronousand Interrupt
• One AsynchronousSchedule
• Maintains all Bulk and Control
• Each explicitly enabled via System software
• Execution Rules
• Repeat each micro-frame
• Periodic schedule first, then
• Asynchronous schedule

Periodic Schedule
Asynchronous Schedule
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Periodic Schedule Overview
Periodic Frame List

• Binary-tree structure
• Traversal from leaf level to root
• Frame List is the Leaf level
• Each level in tree is a poll rate interval
• Objects linked relative to the Frame List, at
  correct poll rate level.
• Schedule includes
• HS/FS/LS Interrupt,
• HS Isochronous,
• FS Isochronous

Poll Rate N ? 1
Periodic List Base Frame Index123 Current
Frame offset
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Periodic Frame List
Periodic Frame List

• Array of schedule object pointers
• Represents a rolling windowof time
• Each location is base pointer forone frames
  worth of work(8 micro-frames)
• Frame work for establishingtime-oriented
  reachability
• HC builds an offset into the Periodic Frame list
  from
• Periodic frame list base address
• Frame Index Register 123
• Increments once each frame (1ms)

To schedule graph

Accesses same offset 8 micro-frames before
preceding to next location
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12
11
2
3
0
12
31
13
12
Frame List Base
Frame Index
Micro-frame select
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Periodic Split Transactions

• Used to service data streams through TT periodic
  pipeline(s)
• Requirement on Host is to
• Execute starts and completes when they need to
  occur
• System software must budget execution footprint
  (starts/completes)
• Host controller must execute and track progress
  of split transaction
• Each endpoint data structure contains
• Micro-frame masks which encode when to execute
  Starts Complete splits
• Micro-state to track progress (to detect lost
  data, etc.)
• Projection of core-spec bus frame boundaries into
  the host schedule created many scheduling
  boundary conditions, so

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Bus Frame View Vs. Host Frame View

• In order to simplify host for TT periodic
  pipeline support
• Host view of frame boundaries is shifted one
  micro-frame from Bus view

HC Periodic Sched.

HS/FS/LS Bus

Frame Boundaries

Frame Boundaries

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0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

HC Periodic
Schedule
Micro
-
frames

CS

CS

CS

CS

SS

CS

CS

CS

CS

SS

Full/Low-SpeedTransaction
Full/Low-SpeedTransaction
7

0

1

2

3

4

5

6

7

0

0

1

2

3

4

5

6

7

0

1

HS Bus
B
-
Frame N

B
-
Frame N1

Frames
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FS/LS Interrupt INFrame-wrap Example
H-Frame
0
1
2
3
4
5
6
7
0
1
2
SS
0
1
2
3
4
5
6
7
0
1
7
B-Frame
Start-Mask 40h Complete-Mask 03h
Must be reachable from consecutive Frame list
locations 0,1, 8,9, 16,17 (poll period of 8)
Queue Head
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FS Isochronous INFrame-Wrap Example
H-Frame X1
H-Frame X
0
1
2
3
4
5
6
7
0
1
2
SS
0
1
2
3
4
5
6
7
0
1
7
B-Frame Y1
B-Frame Y
siTDX
siTDX1
Start-Mask 08h Complete-Mask C3h
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Async. Schedule Overview

• Supports HS/FS/LS Bulk/Control endpoints
• Utilizes split transactions for FS/LS
• Simple, circular linked list
• Yields Round-Robin Service Order
• One bus transaction per list element per
  traversal
• Queue Heads only valid data structure in schedule
• Shuts-down traversal when schedule is empty

Current qHead Pointer
I/O RegisterAsynchronous List Pointer
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Asynch Split Transactions

• Same as HS execution model with
• Micro-machine extension to track split
  transaction
• FS/LS transfer advancement occurs when entire
  split transaction is complete
• e.g. All start-split and complete-split bus
  transactions
• Endpoint speed encoding in schedule data
  structure directs HC to use split protocol

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Agenda

• EHCI Development Overview
• EHCI Architecture/Key Features
• USB 2.0 Host Controller Architecture
• EHCI HC Interface Architecture
• Updates for revision 0.96
• USB2 Host Controller Compliance Program
• Summary

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Updates for Revision 0.96

• Editorial/Clarifications
• Update to Fix 0.95 Erratum
• ERR handshake for FS/LS Interrupt
• New Features
• Support for FS/LS Interrupts that get allocated
  an execution footprint that spans an H-Frame
  boundary
• Rebalance Lockout
• Asynchronous Park-Mode
• BIOS/OS Handoff Support
• In review with Licensees

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0.96 ERR Handshake

• EHCI reloads transaction error counter after
  every good bus transaction
• For FS/LS Interrupts, an ERR handshake decrements
  the error counter, but
• The retry start-split succeeds and reloads the
  transaction error counter
• Result possible endless retry of error condition
• FIX Reload transaction error counter only when
  split transaction completes

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0.96 Interrupt Frame-Wrap

• Binary-tree structure of periodic schedule
  isefficient model
• Natural structure for efficiently managing bus
  bandwidth
• FS/LS Frame-wrap cases stress model efficiency
• Unable to efficiently utilize bandwidth load
  spreading
• Any FS/LS interrupt with SS in H-frame 5 is
  promoted topoll rate 1
• Difficult for system software to manage
• FIX Add back-pointer mechanism to allow HC to
  reach data structures for endpoints budgeted with
  frame-wrap

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0.96 Interrupt Frame-Wrap
8
7
8I.0
4
4
2
8
6
4D.0
4D.1
8H.0
2B.0
8
5
4
4
8G.0
8
4C.0
4C.1
4
1
8F.0
8
1A.0
3
FIX adding specific routing information data
structures to allow system software to describe
required flow to HC
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4
4
8D.0
8
4B.0
4B.1
4B.2
2
8C.0
8
1
2
4
4
4
8B.0
2A.0
8
4A.0
4A.1
4A.2
0
8A.0
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0.96 Rebalance Lockout

• Changes in active endpoints below a Transaction
  Translator
• System software recalculates TT budget
• Active endpoints may require rebalancing
• New start- and complete-split masks
• Difficult for System Software to manage rebalance
• FIX Add handshake to deactivate FS/LS queueson
  command
• Software sets new bit that tells HC to deactivate
  before starting another split transaction
• Very easy for system software to detect when data
  structure is safe to update, then reactivate

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0.96 Asynch Park-Mode

• Asynchronous schedule traversal rules require one
  bus transaction per list element, per traversal
• Round-robin service required for FS/LS
  bulk/control
• Traversing data structures is pure overhead
• Large contributor to inter-transaction times on
  USB
• Reduces actual number of bus-transactions and
  effective throughput
• FIX Allow HC to Park on HS endpoint and
  execute more than one bus transaction
• Provides potential for reducing average
  inter-transaction times, increasing throughput

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0.96 BIOS/OS Handoff

• When BIOS uses EHCI,
• Need graceful hand-off of controller when OS
  loads
• Ignored in 0.95 because legacy support can be
  provided completely by BIOS and companion
  controllers
• Support already defined
• Need mechanism defined for final specification
• FIX define simple host controller mechanism to
  help hand-off of host controller ownership

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Agenda

• EHCI Development Overview
• EHCI Architecture/Key Features
• USB 2.0 Host Controller Architecture
• EHCI HC Interface Architecture
• Updates for revision 0.96
• USB2 Host Controller Compliance Program
• Summary

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EHCI Compliance Program
USB 2.0 Hub Testing
USB 2.0 Electrical (HS/FS/LS)
EHCI Compliance
EHCI-specific Functional Testing
EHCI Compliance Test Suite
Inter-Operability Tests
Standard USB 2.0 Compliance Tests
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EHCI Compliance Testing

• EHCI Compliance Test Suite
• Evaluates HC Conformance to specification
• EHCI Test Specification, rev. 1.0
• EHCI Compliance Testing Software
• Standardized Compliance Devices
• Inter-Operability Testing
• Evaluates HC Operability in Real Environment
• Uses standard Microsoft USB Stack
• Off-the-shelf devices (USB-certified) w/their
  device drivers
• USB 2.0 Certified Hub(s)

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Inter-Operability Testing

• Device Mix
• All off the shelf
• High, Full, and Low-speed
• USB 2.0 and 1.1 Hubs
• Bulk, Control, Interrupt and Isochronous
• Test matrix of typical configurations and loads
• Pass/Fail Criteria are fairly simple does it
  run?

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EHCI Test Methodology

• Test Specification derived from EHCI
  Specification
• Test Assertions
• Short, concise, unambiguous statement. Derived
  from specification
• Test Descriptions
• Outlines test, pass/fail criteria and which
  assertions are exercised

Test Assertions
EHCI Specification
EHCI Compliance Tests
EHCI Test Specification
Test Descriptions
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EHCI Compliance Software
Results Log
Test Executive

• Test Executive
• Test sequencing, results logging, etc.
• Test DLLs
• 11 correspondence to tests defined in EHCI Test
  Specification
• Testing Services DLL
• Simplifies details of developing/maintaining
  tests
• Special-purpose host controller driver

EHCI Tests
Test Services
Compliance HCD
EHCI Under Test
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Compliance Device Req.

• Features
• All transfer types ( for enumerated speed)
• High-bandwidth (high-speed only devices)
• One or more Data loop back endpoints
• For all transfer types supported, incl. hbw (not
  concurrently)
• Data streaming with no Naks
• Infinite sink, source, or loop back
• Min to Max packet
• Always Nak, Stall, Timeout and/or generate CRC
  Error
• Programmable disconnect, resume and reconnect

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Compliance Device I/F

• Device exports endpoint capabilities to host
• Host can reconfigure endpoint characteristics to
  test requirements
• Based on endpoint capabilities exported by the
  device
• Host can extract testing counters
• Disconnect/Delay/Reconnect
• Remote-wakeup Delay

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Example Test Scenario

• Test LS/FS Interrupt-IN
• Use loop-back endpoints
• Many errors can be detected as mis-compares
• Use Schmoo IN endpoint
• Out endpoint simply used to stage expected
  dataat device
• Data payload in Schmoo IN adjusted to move IN
  endpoint data packet across a micro-frame
  boundary
• Exercise all combinations of delivering data in
  first and second micro-frame
• Test repeated for each valid micro-frame boundary

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Example Test Scenario

• Step 1 send OUT data to loop back OUT endpoint
• Step 2 start schmoo-IN with first data payload
• Step 3 start loop back IN to start in same
  micro-frame after schmoo-IN
• Check data, check bus analyzer
• Make schmoo-IN one bit longer, and repeat

0
1
2
3
CS1
SSlbi
CS0
SSsxhmoo
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Agenda

• EHCI Development Overview
• EHCI Architecture/Key Features
• USB 2.0 Host Controller Architecture
• EHCI HC Interface Architecture
• Updates for revision 0.96
• USB2 Host Controller Compliance Program
• Summary

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Summary

• Healthy, proven specification
• Reasonable tradeoff of hardware/software
  complexity
• Several implementations under evaluation
• Meeting stated goals
• 0.95 Implementations identified errata
• Update to spec for errata is coming
• Compliance program is gaining momentum
• Test specification at revision 1.0
• Test software infrastructure established
• Tests under development

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Summary
Continued

• Dates of Interest
• 0.96 EHCI Revision available in Q201
• Alpha-quality HC Compliance Test Suite
  availableto Licensees in Q301
• 1.0 EHCI Revision available in first half of 02
• Gating item is validation of integrated host
  controller
• Contacts/URLs
• Questions on Specification and/or Licensing
• ehcisupport_at_intel.com
• Specification, Documentation, etc.
• http//developer.intel.com/technology/usb

Note all dates provided are for planning
purposes only and are subject to change