Analog Signal Capture Using FPGA and USB Interface

1
Analog Signal Capture Using FPGA and USB Interface

• Robert C DeMott II
• Jeremy A Cooper

2
Outline

• Project Hardware Overview
• Brief USB Protocol Overview
• Cypress USB Peripheral Controller
• Digilent USB Protocol
• Digilent Data Transfer Example VHDL
• Modified Data Transfer VHDL
• ADC Hardware
• ADC Driver
• Block FIFO Implementation
• Modified USB Protocol for ADC
• C PC Application

3
Project Overview

• Transfer sampled ADC data over USB to PC
  Application
• Run ADC at 1 million samples per second
• USB transfer must be at least 2MB/s
• USB communication using Nexys2 Board and Cypress
  chip
• PC Application written in C using Digilent
  communication driver

4
Hardware

• Windows PC
• Digilent Nexys2 Board
• Cypress CY7C68013A High-Speed USB Peripheral
  Controller
• Digilent FX2 Module Interface Board
• Analog Control System Board
• Analog Devices AD7980 ADC
• TLA721 Tektronix Logic Analyzer Mainframe (for
  testing)

5
System Block Diagram
6
USB ADC System
7
USB Protocol Overview

• USB is a serial protocol involving one host and
  multiple peripherals in a star topology
• USB communication based on logical channels
  between the host controller and an endpoint,
  called a pipe
• An endpoint is a logical entity on the peripheral
  device
• Multiple endpoints are grouped into interfaces
• Each endpoint is unidirectional
• When a USB device is connected to a host, the
  enumeration process occurs to assign it a unique
  7-bit address
• Device drivers are optionally loaded on the host
  and the device is set to a configured state

8
USB Protocol Overview

• USB cables use half duplex differential signaling
  in a twisted pair data cable
• The host polls the bus periodically for traffic
• Host controller initiates all communication and
  must explicitly request data from a peripheral
• All data is transmitted in packets
• Bit stuffing is performed on strings of 1s, so
  certain bit strings take longer to transmit
• Each packet may containbetween 0 1024 bytesin
  the payload

9
USB Subsystem
10
CY7C68013A Capabilities

• USB 2.0 high-speed certified
• 8 or 16 bit external data interface
• 4 programmable endpoints
• GPIF (General Programmable Interface)
• Integrated enhanced 8051
• Up to 48MHz CPU operation
• 4 clocks per instruction cycle
• I2C Controller
• 4 Integrated FIFOs

11
CY7C68013A Block Diagram
12
Cypress Chip Operating Modes

• There are 3 modes of operation of the FX2
• Port I/O
• Use the internal 8051 to process USB data
  directly
• Slave FIFO
• Endpoint FIFOs are controlled by an external
  master
• GPIF (General Programmable Interface)
• GPIF acts as an internal FIFO master when
  connected to external logic that doesnt have a
  standard FIFO interface

13
Cypress Chip Operating Modes

• Digilent seems to use the slower Port I/O Mode
• Slave FIFO Mode is best for high speed transfer
  (in Auto Mode)

14
Enable Higher Speed Transfers

• Enable Slave FIFO mode and AUTOIN and AUTOOUT for
  IN/OUT endpoints
• AUTOIN When complete packet arrives from FPGA,
  immediately/automatically send to USB domain
  (bypass 8051)
• AUTOOUT When complete packet arrives from host,
  immediately/automatically send to interface
  domain (bypass 8051)
• Uses multi-buffered quantum FIFOs to improve
  transfer speeds

15
Slave FIFO Synchronous Write Timing
16
Slave FIFO Synchronous Read Timing
17
Cypress Nexys2 USB Interface
Cypress CY7C68013A
18
Cypress Nexys2 USB Interface

• The Cypress chip enables the following features
  on the Nexys2
• Provide power over USB (up to 500mA)
• Program FPGA by emulating JTAG over USB
• General purposeuser-data transfers
• Ability to overwritefirmware bypassDigilents
  protocol(hardware modification)

19
Nexys2 USB Interface

• 8 Bidirectional Data Pins
• 6 Control Pins
• Write 0write to FPGA, 1read from FPGA
• Address Strobe 0read/write from/to address
  register
• Data Strobe 0read/write from/to data register
• Wait 1ready to read/write data, 0transfer
  cycle complete
• Interrupt Reset pins are not used in this
  design
• Clock Pin
• Other miscellaneous Cypress Pins

20
Nexys2 USB Schematic
21
Digilent USB Protocol

• Digilent has custom firmware on the CY7C68013A to
  emulate a PC parallel port using EPP (Enhanced
  Parallel Port) protocol
• Uses 1 address register a set of 8-bit wide
  data registers
• Communication is done in 4 transfer cycle types
• Address Read
• Address Write
• Data Read
• Data Write
• Data read or write cycles read from (write to) a
  register specified by address register

22
Digilent Address Write/Read
Address Write (PC-gtFPGA)
Address Read (FPGA-gtPC)
23
Digilent Data Write/Read
Data Write (PC-gtFPGA)
Data Read (FPGA-gtPC)
24
Digilent Example VHDL

• Modified example from Echelon Embedded designed
  specifically for Nexys2
• Contains several registers
• LEDs (0x00)
• Switches (0x01) (read-only)
• Buttons (0x02) (read-only)
• SSD (0xFF0xFE)
• Reads or writes data and address registers based
  on state machine

25
Digilent USB Protocol State Machine

• Machine contains 3 inputs
• Astb address strobe (active low)
• Dstb data strobe (active low)
• Pwr write pin (1FPGA-gtUSB, 0USB-gtFPGA)
• Machine contains 4 outputs
• Awr write address (internal variable)
• Dwr write data (internal variable)
• Dir data direction (1FPGA-gtUSB, 0USB-gtFPGA)
• Wait wait pin (synchronization signal)

26
Digilent USB Protocol State Machine
27
State Machine Definition

• constant stEppReady std_logic_vector(7 downto
  0) "0000" "0000"
• constant stEppAwrA std_logic_vector(7 downto
  0) "0001" "0000"
• constant stEppAwrB std_logic_vector(7 downto
  0) "0010" "0100"
• constant stEppAwrC std_logic_vector(7 downto
  0) "0011" "0001"
• constant stEppArdA std_logic_vector(7 downto
  0) "0100" "0010"
• constant stEppArdB std_logic_vector(7 downto
  0) "0101" "0010"
• constant stEppArdC std_logic_vector(7 downto
  0) "0110" "0011"
• constant stEppDwrA std_logic_vector(7 downto
  0) "0111" "0000"
• constant stEppDwrB std_logic_vector(7 downto
  0) "1000" "1000"
• constant stEppDwrC std_logic_vector(7 downto
  0) "1001" "0001"
• constant stEppDrdA std_logic_vector(7 downto
  0) "1010" "0010"
• constant stEppDrdB std_logic_vector(7 downto
  0) "1011" "0010"
• constant stEppDrdC std_logic_vector(7 downto
  0) "1100" "0011"
• --4 MSbits are state number
• --4 LSbits are outputs in the following order
• -- Dwr, Awr, Dir, Wait

28
Output Bus Assignment

• busEppData lt regLed when regEppAdr
  x"00" else
• rgSwt when regEppAdr
  x"01" else
• "000" rgBtn when regEppAdr
  x"02" else
• regUsr1 when regEppAdr
  x"FE" else
• regUsr2 when regEppAdr
  x"FF" else
• "00000000"
• busEppOut lt regEppAdr when Astb '0' else
  busEppData
• pdb lt busEppOut when Pwr '1' and Dir '1'
  else "ZZZZZZZZ"
• --pdb is the tristate data bus
• --regEppAdr is the address register
• --other reg or rg are the registers for the
  buttons, LEDs, switches, SSD
• --Pwr is the write pin
• --Dir is the data direction (1FPGA-gtUSB,
  0USB-gtFPGA)

29
Modified State Machine

• Several problems with the original design
• The extra states are unnecessary when using the
  48MHz USB clock
• The state and variable names are unintelligible
• Only a handful of registers are actually used in
  the address space
• We modified the state machine and the register
  set to read from (write to) BRAM

30
Improved USB State Machine

• Machine contains 3 inputs
• addressStrobePin address strobe (active low)
• dataStrobePin data strobe (active low)
• fpga2UsbPin write pin(1FPGA-gtUSB, 0USB-gtFPGA)
• Machine contains 6 outputs
• OutputEnable output enable
• WaitOutput wait output pin
• AddressDataMux (0output address, 1output data)
• RamWriteEnable enable writing to BRAM
• AddressUpdateEnable update address register
• RamReadEnable enable reading from BRAM

31
Improved USB State Machine
32
Modified State Machine BRAM

• type state_type is (s0_Ready,s1_Fpga2Usb_Data,
  s1_Fpga2Usb_Address,s1_Usb2Fpga_Data,
  s1_Usb2Fpga_Address,s2_Fpga2Usb_Data,
  s2_Fpga2Usb_Address,s2_Usb2Fpga_Data,
  s2_Usb2Fpga_Address)
• signal currentState state_type s0_Ready
• signal nextState state_type s0_Ready
• attribute fsm_encoding string
• attribute fsm_encoding of currentState signal
  is "auto"
• attribute safe_implementation string
• attribute safe_implementation of currentState
  signal is "yes"
• --256 bytes ram
• type ram_type is array(0 to 255) of
  std_logic_vector(7 downto 0)
• signal testRam ram_type (others gt (others
  gt '0'))

33
Modified Data Assignments

• MemoryProcess process(usb_clock) --ram
  control process
• begin
• if(rising_edge(usb_clock)) then
• if(ramWriteEnable '1') then
• testRam(conv_integer(usbAddressRegist
  er)) lt dataIn
• end if
• if(ramReadEnable '1') then
• dataOut lt testRam(conv_integer(usbAd
  dressRegister))
• end if
• end if
• end process
• AddressProcess process(usb_clock)
• begin
• if(rising_edge(usb_clock)) then
• if(addressUpdateEnable '1') then
• usbAddressRegister lt dataIn
• elsif(ramWriteEnable '1' or
  ramReadEnable '1') then
• usbAddressRegister lt
  usbAddressRegister 1

34
Analog to Digital Conversion
35
Analog Capture Board

• External PCB containing Op Amps and ADCs used to
  acquire analog data.
• Designed to test various analog filter components
  and configurations for VCUs next generation
  flight control system.
• System will ultimately be used to interface
  several analog sensors (barometric pressure,
  infrared, etc) with the FCS.
• Board contains four similarly designed quadrants.

36
Analog Capture Board

• Each quadrant contains
• 8 buffered analog input channels (0 to 5V)
• 8 low pass anti-aliasing filters (2-pole Bessel
  configuration)
• 8 to 1 channel analog multiplexer (MAX4617)
• Low noise, 1MSps 16-bit ADC (AD7980)
• Low noise voltage references regulators (2.5V,
  5.0V and 5.5V)

37
Analog Capture Board
38
FX2 Interface Module

• The Digilent FX2 interface module is used to
  connect the analog capture board with the Nexys2.
• This module also provides connections for logic
  analyzer probes used to debug the system.

39
Analog to Digital Converter

• Analog Devices AD7980
• 16-bit Successive Approximation Analogto
  Digital Converter
• 1 Million Samples per Second
• Integral Non-Linearity 1.25 LSB Max
• Signal to Noise and Distortion 91.25dB.
• Low power dissipation 7.0mW Max
• Simple Serial Interface (SPI Based)

40
ADC Serial Interface

• Signals
• SCK Serial Data Clock
• CNV Conversion Start Signal (SPI Chip Select)
• SDO Serial Data Output (SPI Master-In,
  Slave-Out)
• Description
• A rising edge on CNV initiates a conversion and
  forces SDO to high impedance.
• CNV should remain high until the maximum
  conversion time elapses.
• When the conversion is complete, the AD7980
  enters the acquisition phase and powers down.
• When CNV goes low, the MSB is output onto SDO.
  The remaining data bits are then clocked by
  subsequent SCK falling edges.
• After the 16th SCK falling edge or when CNV goes
  high, whichever is earlier, SDO returns to high
  impedance.

41
ADC Serial Interface
42
Timing Specifications

• Conversion Time (tCONV) 500-710 ns
• Acquisition Time (tACQ) 290-500 ns
• Cycle Time (tCYC) 1000 ns minimum (1MSps)
• Clock Period (tSCK) 12 ns minimum (83.33MHz)
• For 1MSps throughput, maximum clock period is
  (tCYC-tCONV,MAX)/16 290/16 18.125 ns
• Minimum clock frequency is 55.17MHz
• Next integer multiple of 1MHz is 56MHz
• Clock frequencies from 56MHz to 83MHz should work
• However

43
Timing Specifications

• ADC Clock Falling Edge to Old Data Invalid
  (tHSDO) 3 ns
• ADC Clock Falling Edge to New Data Valid (tDSDO)
  11 ns
• Spartan 3 3E I/O Delay (Measured) 2.5 ns
• This results in a round trip delay of 16 ns.
• This effectively limits the serial clock
  frequency to between 56MHz and 62MHz (assuming
  1MSps is desired).
• Faster clock speeds could theoretically be used
  by increasing the Spartan 3Es IBUF_DELAY_VALUE
  parameter and pipelining

44
FPGA Logic
45
FPGA Logic (ADC Driver)
46
ADC Driver

• A custom VHDL entity was created to control the
  ADC and analog multiplexer.
• Clock frequency and desired sample rate can be
  specified using generics.
• A simple linear state machine controls the
  conversion / acquisition process.
• Each state lasts a fixed number of clock cycles.
• The number of clock cycles for each state are
  determined at compile time
• A counter process is used to control state
  transitions.

47
ADC Driver State Machine

• Simple three-state Mealy Machine.
• Contains the following states
• STARTUP Initialization state. Used during reset
  to ensure that the ADC itself is in a known
  state. Stays in this state for at least 1000 ns
  (1 complete sample period).
• CONV_WAIT Wait state for ADC conversion phase.
  Remains in this state for at least 710ns. The
  multiplexer channel is incremented at the end of
  this state.
• ACQ_SHIFT Acquisition state. Data is serially
  shifted out of the ADC and into an internal shift
  register. This state is always 16 clock cycles.
  The resulting sample data is stored at the end of
  this state.

48
ADC Driver State Machine

• The state machine has the following input
• TimerPulse Instructs state machine to transition
  states.
• The state machine has the following outputs
• Convert Instructs ADC to begin an analog to
  digital conversion.
• ClockEnable Enable signal for the serial clock
  tri-state buffer.
• SampleValid Status flag indicating that the
  shift register contains a complete sample.
  External logic monitors this signal and copies
  the sample to memory when SampleValid goes high.
• IncrementMux Control flag instructing an
  up-counter to increment the analog multiplexer
  channel select signal.

49
ADC Driver State Machine
50
ADC Driver Parameters

• The clock frequency and desired sample rate are
  passed in as VHDL generics.
• ADC_CLK_FREQ 60_000_000
• SAMPLE_RATE 1_000_000
• The number of clock cycles for the STARTUP and
  CONV_WAIT states are automatically calculated at
  compile time based on these generics.
• Assert statements are also used to ensure valid
  values are entered and that ADC timing
  requirements are met.

51
ADC Driver Constants

• -- Period of each complete convert acquire
  cycle.
• constant SAMPLE_PERIOD real 1.0/SAMPLE_RATE
• -- Number of clock cycles spent in the
  acquisition state.
• constant ACQ_CYCLES real 16
• -- Time spent in the acquisition state.
• constant ACQ_TIME real ACQ_CYCLES/ADC_CLK_FRE
  Q
• -- Time spent in the conversion state.
• constant CNV_TIME real REALMAX(710.0e-9,
• SAMPLE_PERIOD -
  ACQ_TIME)
• -- Number of clock cycles spent in the conversion
  state.
• constant CNV_CYCLES real ceil(CNV_TIME
  ADC_CLK_FREQ)
• -- Total number of cycles per sample.
• constant SAMPLE_CYCLES real (ACQ_CYCLES
  CNV_CYCLES)

52
ADC Driver Counter

• A synchronous up-counter is used to control state
  transitions.
• The output of the counter is compared with a
  value based on the current state (auto-computed
  from VHDL generics).
• When the counter reaches the compare value a
  terminal pulse is generated.
• This pulse automatically resets the counter and
  triggers a state transition.
• The state transition causes the next
  auto-computed compare value to be loaded.

53
ADC Driver Counter

• TimerProcess process(CLK)
• begin
• if ( Rising_Edge(CLK) ) then
• if ( RST '1' or TimerPulse '1' ) then
• TimerValue lt (others gt '0')
• else
• TimerValue lt TimerValue 1
• end if
• end if
• end process
• TimerPulse lt '1' when (TimerValue
  TimerCompare) else '0'
• TimerCompare_Mux process(CurrentState)
• begin
• case (CurrentState) is
• when ADC_IDLE_WAIT gt
• TimerCompare lt IDLE_WAIT_TIMER_COMP
• when ADC_CONV_WAIT gt

54
ADC Driver Block Diagram
55
ADC Driver Clock Signals

• The internal FPGA logic and the external serial
  clock both run at 60MHz.
• The internal logic is rising edge sensitive.
• The ADC serial logic is falling edge sensitive.
• Two separate clocks are used one being 180
  degrees out of phase with the other (inverted).
• A Xilinx DCM is used to generate both 60MHz
  clocks from the 50MHz system clock.
• This allows both clock signals to be globally
  routed using dedicated clock nets.
• This also avoids the delay that would result if
  logic were used to perform the inversion.

56
ADC Driver Clock Signals
57
ADC Driver Clock Signals

• The serial clock is only enabled during the
  acquisition state.
• During the conversion state, the clock signal is
  held low.
• This helps reduce digital noise while the ADC is
  sampling.
• The tri-state buffer in the Spartan 3E output
  block is used along with an internal pulldown
  resistor to accomplish this.
• This method avoids routing the clock through
  internal logic (lookup tables) and thus prevents
  clock skew.

58
FPGA Clock Domains

• This design contains two different clock domains.
• 60MHz Clock for ADC Control Logic
• 48MHz Clock for USB Control Logic
• A synchronization method is needed to pass data
  between the clock domains while avoiding
  metastability issues.
• For single-bit signals, this is as simple as
  using two cascaded flip-flops.
• For multi-bit signals, more complex logic is
  necessary.

59
FPGA Clock Domains

• One possible synchronization method
• A multi-bit memory element can be utilized to
  store one or more data words that need to cross
  domains.
• Data is written to the memory element until it is
  filled.
• Once filled, a status signal is generated in the
  write domain and transferred to the read domain
  using the cascaded flip-flop method.
• Data is then read until the memory element is
  empty.
• An acknowledge signal is then generated and
  passed back to the write domain.
• The dual-ported nature of the Xilinx BRAM makes
  it well suited for this purpose.

60
Block FIFO

• This method can be extended by utilizing multiple
  blocks of memory.
• Read/Write status signals exist for each block of
  memory.
• When one block of memory is filled, the write
  domain sets the appropriate status bit and moves
  on to the next block.
• Similarly, the read domain empties a block at a
  time, and acknowledges each complete read.
• This creates a multi-block FIFO structure similar
  to the one in the Cypress USB chip.
• This method is used to transfer blocks of samples
  from the ADC clock domain to the USB clock
  domain.
• The block size was chosen to be an integer
  multiple of the USB packet size (512 bytes).
• A total of 32KB of Block RAM was dedicated to
  this purpose.

61
Block FIFO
62
Block FIFO

• Read Signals
• ReadCLK Clock signal used to control the data
  read logic.
• ReadNext Read next signal. The read pointer is
  incremented and the next unit of data will be
  output on the rising edge of ReadCLK. One unit
  of data can be removed from the FIFO every clock
  cycle if this signal is connected to
  ReadDataValid.
• ReadDataValid Status signal if this signal is
  high, ReadData contains valid data to be read.
• ReadError Status signal if this signal is high,
  a read was attempted on an empty FIFO.
• ReadData Data output signal. 16 bits wide.

63
Block FIFO

• Write Signals
• WriteCLK Clock signal used to control the data
  write logic.
• WriteEnable Write enable signal. One unit of
  data can be added to the FIFO on every rising
  edge of WriteCLK that this signal is high.
• WriteReady Status signal if this signal is
  high, there is free space in the FIFO to store
  data.
• WriteError Status signal if this signal is
  high, a write was attempted when the FIFO was
  full.
• WriteData Data input signal. 16 bits wide.

64
USB I/O
65
Digilent USB (ADC Version)

• Digilent USB State Machine was modified to
  control the ADC Driver and continuously stream
  ADC samples to the PC (16Mbps).
• The address write functionality was replaced with
  a command register structure.
• The read data functionality was redesigned to
  extract 16-bit data samples from the FIFO.
• The write data and read address modes are
  unnecessary and were replaced with dummy states
  (read/write zeros).

66
USB State Machine

• State Machine contains the following inputs
• USB_Direction Specifies direction of USB
  transfer (1FPGA-gtUSB, 0USB-gtFPGA).
• USB_AddrStrobe Address Strobe (active low). Used
  to write data to the command register when
  USB_Direction 0.
• USB_DataStrobe Data strobe (active low). Used
  to read samples from the Block FIFO when
  USB_Direction 1.
• ADC_GettingData Status flag indicating whether
  data should be retrieved from the Block FIFO.
• ReadingDataMSB Status flag indicating whether
  the MSB or LSB of ADC sample should be output.
• FIFO_ReadDataValid Status flag indicating
  whether more samples are available to be read
  from the Block FIFO.

67
USB State Machine

• State Machine contains the following outputs
• OutputEnable Output enable for USB data bus
  (active high, tri-state control).
• WaitOutput Wait output pin (active high).
• OutputDataMux Control flag indicating whether to
  output sample data (1) or dummy data (0) to bus.
• CommandUpdate Control flag indicating if
  incoming data should be stored to the command
  register (active high).
• ReadDataMSB Control flag indicating that a
  sample should be read from the FIFO and the MSB
  should be output to the data bus (active high).
• ReadDataLSB Control flag indicating that the
  previously stored LSB should be output to the
  data bus (active high).

68
USB State Diagram
69
USB Commands

• The following commands were implemented
• CMD_StopADC Disables the ADC and Block FIFO by
  holding the Reset signal high.
• CMD_StartADC Enables the ADC and Block FIFO by
  bringing the Reset signal low.
• CMD_GetSamples Specifies that subsequent read
  data operations will return ADC samples from the
  FIFO.
• CMD_SetChannel Can be used to override the
  analog multiplexer channel used. The selected
  channel and override flag are stored in the upper
  nibble of the command byte.

70
USB Command Parsing

• CommandParseProcess process(USB_CLK)
• begin
• if ( Rising_Edge(USB_CLK) ) then
• case(usbCommandRegister(CMDRange)) is
• when CMD_StopADC gt
• ADC_Running lt '0'
• ADC_GettingData lt '0'
• when CMD_StartADC gt
• ADC_Running lt '1'
• ADC_GettingData lt '0'
• when CMD_GetSamples gt
• ADC_Running lt ADC_Running
• ADC_GettingData lt ADC_Running
• when others gt
• ADC_Running lt ADC_Running
• ADC_GettingData lt ADC_GettingData
• end case
• end if
• end process

71
Multiplexer Control Process

• MuxControlProcess process(USB_CLK)
• begin
• if ( Rising_Edge(USB_CLK) ) then
• case(usbCommandRegister(CMDRange)) is
• when CMD_StartADC gt
• MUX_Channel_i lt usbCommandRegister(MUXRange)
  
• MUX_Override_i lt usbCommandRegister(MUXOverri
  deBit)
• when CMD_SetChannel gt
• MUX_Channel_i lt usbCommandRegister(MUXRange)
  
• MUX_Override_i lt usbCommandRegister(MUXOverri
  deBit)
• when others gt
• MUX_Channel_i lt MUX_Channel_i
• MUX_Override_i lt MUX_Override_i
• end case
• end if
• end process

72
Data Control Process

• DataProcess process(USB_CLK)
• begin
• if ( Rising_Edge(USB_CLK) ) then
• if ( ADC_Running '0') then
• DataOut lt (others gt '0')
• DataLSB lt (others gt '0')
• ReadingDataMSB lt '0'
• elsif ( ReadDataMSB '1' ) then --only read
  from FIFO in MSB read state
• DataOut lt FIFO_ReadData(15 downto 8)
• DataLSB lt FIFO_ReadData(7 downto 0) --store
  LSB for next USB transfer
• ReadingDataMSB lt '1'
• elsif ( ReadDataLSB '1' ) then
• DataOut lt DataLSB
• DataLSB lt DataLSB --transfer the stored LSB
  and don't read from FIFO
• ReadingDataMSB lt '0'
• else
• DataOut lt DataOut
• DataLSB lt DataLSB
• ReadingDataMSB lt ReadingDataMSB

73
USB ADC Control
74
Digilent DPCUtil API

• For PC applications to communicate using the
  Digilent protocol, use dpcutil.dll that comes
  with the Adept Software Suite
• API DLL written in MS Visual C 6.0
• For use in C, a DLL wrapper is required
• First step is initialization with DpcInit()
• Last step is termination with DpcTerm()
• Wrapper and ADC read code was written using MS
  Visual Studio 2005 in C

75
Digilent Port Communications Wrapper

• static class DPCUtil
• // DPC Stuff
• DllImport("dpcutil.dll")
• public static extern bool DpcInit( out int
  ErrorCode )
• DllImport("dpcutil.dll")
• public static extern void DpcTerm()
• DllImport("dpcutil.dll")
• public static extern bool DpcGetDpcVersion(
  StringBuilder VersionString, out int ErrorCode )
• DllImport("dpcutil.dll")
• public static extern bool DpcStartNotify( IntPtr
  hwndTemp, ushort idNotifyTemp, out int ErrorCode
  )
• DllImport("dpcutil.dll")
• public static extern bool DpcEndNotify( IntPtr
  hwndTemp, out int ErrorCode )
• DllImport("dpcutil.dll")
• public static extern bool DpcGetVersion( IntPtr
  InterfaceHandle, byte rgbVersion, int
  cbVersion, out int ErrorCode, UIntPtr
  TransactionID )
• DllImport("dpcutil.dll")
• public static extern int DpcGetFirstError(
  IntPtr InterfaceHandle )

BOOL DpcGetDpcVersion (char szVersion, ERC
perc)
76
DPC Wrapper

• // Data Transfer Stuff
• DllImport("dpcutil.dll")
• public static extern bool DpcOpenData( out IntPtr
  InterfaceHandle, StringBuilder DeviceName, out
  int ErrorCode, UIntPtr TransactionID )
• DllImport("dpcutil.dll")
• public static extern bool DpcCloseData( IntPtr
  InterfaceHandle, out int ErrorCode )
• DllImport("dpcutil.dll")
• public static extern bool DpcPutReg( IntPtr
  InterfaceHandle, byte Address, byte Data, out int
  ErrorCode, UIntPtr TransactionID )
• DllImport("dpcutil.dll")
• public static extern bool DpcGetReg( IntPtr
  InterfaceHandle, byte Address, out byte Data, out
  int ErrorCode, UIntPtr TransactionID )
• DllImport("dpcutil.dll")
• public static extern bool DpcPutRegRepeat( IntPtr
  InterfaceHandle, byte Address, byte DataArray,
  int DataLength, out int ErrorCode, UIntPtr
  TransactionID )
• DllImport("dpcutil.dll")
• public static extern bool DpcGetRegRepeat( IntPtr
  InterfaceHandle, byte Address, byte DataArray,
  int DataLength, out int ErrorCode, UIntPtr
  TransactionID )

77
Initialization/Termination

• private bool DPC_Init()
• int ErrorCode
• int DeviceID
• if ( !DPCUtil.DpcInit(out ErrorCode) )
• return false
• DeviceID DPCUtil.DvmgGetDefaultDev(out
  ErrorCode)
• if ( DeviceID -1 )
• return false
• else
• DPCUtil.DvmgGetDevName(DeviceID,
  DefaultDeviceName, out ErrorCode)
• return true

78
Read a Register

• public bool DPC_GetReg( byte RegisterAddress,
  ref byte RegisterData )
• int ErrorCode
• IntPtr InterfaceHandle
• bool Success true
• if ( !DPCUtil.DpcOpenData(out InterfaceHandle,
  DefaultDeviceName, out ErrorCode, UIntPtr.Zero) )
• return false
• if ( !DPCUtil.DpcGetReg(InterfaceHandle,
  RegisterAddress, out RegisterData, out ErrorCode,
  UIntPtr.Zero) )
• Success false
• DPCUtil.DpcCloseData(InterfaceHandle, out
  ErrorCode)
• return Success

79
Write a Register

• public bool DPC_PutReg( byte RegisterAddress,
  byte RegisterData )
• int ErrorCode
• IntPtr InterfaceHandle
• bool Success true
• if ( !DPCUtil.DpcOpenData(out InterfaceHandle,
  DefaultDeviceName, out ErrorCode, UIntPtr.Zero) )
• return false
• if ( !DPCUtil.DpcPutReg(InterfaceHandle,
  RegisterAddress, RegisterData, out ErrorCode,
  UIntPtr.Zero) )
• Success false
• DPCUtil.DpcCloseData(InterfaceHandle, out
  ErrorCode)
• return Success

80
Read ADC Data

• private void CaptureThread_DoWork( object sender,
  DoWorkEventArgs e )
• const byte CMD_Stop 0x00
• const byte CMD_Start 0x01
• const byte CMD_GetData 0x02
• BackgroundWorker BW sender as
  BackgroundWorker
• CaptureThreadArguments Args e.Argument as
  CaptureThreadArguments
• FileStream CaptureFile new FileStream(Args.File
  Name, FileMode.Create)
• byte TempData new byteBlockSize
• ulong SampleCount 0
• long CurrentTicks
• long StartTicks
• IntPtr InterfaceHandle
• int ErrorCode
• byte Dummy
• // Open DPC Stuff

81
Read ADC Data

• while ( !BW.CancellationPending SampleCount lt
  Args.TotalSamples )
• ulong SamplesRemaining Args.TotalSamples -
  SampleCount
• int NumBytes (SamplesRemaining gt
  SamplesPerBlock) ? BlockSize (int)(SamplesRemain
  ing2)
• if ( DPCUtil.DpcGetRegRepeat(InterfaceHandle,
  CMD_GetData, TempData, NumBytes, out ErrorCode,
  UIntPtr.Zero) )
• // Save samples
• CaptureFile.Write(TempData, 0, NumBytes)
• SampleCount (ulong)(NumBytes / 2)
• CurrentTicks System.DateTime.Now.Ticks
• // Report the current status of the capture
• CaptureProgressArguments ProgArgs new
  CaptureProgressArguments()
• ProgArgs.LastSample (ushort)((TempDataTempDa
  ta.Length-2 ltlt 8) TempDataTempData.Length-1)
  
• ProgArgs.Ticks (CurrentTicks-StartTicks)
• ProgArgs.Samples SampleCount
• BW.ReportProgress(0, ProgArgs)

82
Read ADC Data

• else
• break
• DPCUtil.DpcGetReg(InterfaceHandle, CMD_Stop,
  out Dummy, out ErrorCode, UIntPtr.Zero)
• DPCUtil.DpcCloseData(InterfaceHandle, out
  ErrorCode)
• if ( BW.CancellationPending )
• e.Cancel true
• CaptureFile.Close()
• CaptureFile.Dispose()

83
Put Register Repeat Example

• Write to register 0x00 4000 times using
  DPC_PutRegRepeat().
• Notice 330us initial delay after writing to
  address register
• 5.2us delay between512 byte chunks
• 156 ns between bytes

84
Get Register Repeat Example

• Read from register 0x00 1000 times using
  DPC_GetRegRepeat().
• Notice 20us initial delay after writing to
  address register
• 4.9us delay between512 byte chunks
• 188 ns between bytes

85
Put Register Repeat Example 2

• Write to register 0x00 256 times using
  DPB_GetRegRepeat() after modifications
• Notice 225us delay after writing to address
  register
• 124ns between bytes now

86
Conclusion

• We successfully implemented a PC-controlled ADC
  reader
• The original Digilent FPGA USB protocol was
  modified and improved
• We are able to continuously read at 16Mbit/s with
  no data corruption
• Speeds up to 50Mbit/s should be possible with the
  improved Digilent protocol
• Even greater speeds can be achieved with new
  firmware on the Cypress chip

87
Sources

• Endpoint FIFO Architecture of EZ-USB FX1/FX2.
  http//www.cypress.com/?docID4704
• EZ-USB FX2LP USB Microcontroller High-Speed USB
  Peripheral Controller. http//www.cypress.com/?doc
  ID5485
• Digilent Parallel Interface Model Reference
  Manual. http//www.digilentinc.com/Data/AppNotes/D
  pimRef.pdf
• Digilent Port Communications Programmers
  Reference Manual. http//www.digilentinc.com/Data/
  Products/ADEPT/DPCUTIL20Programmers2020Referenc
  e20Manual.pdf
• Nexys2_sch.pdf. http//www.digilentinc.com/Data/P
  roducts/NEXYS2/Nexys2_sch.pdf
• Digilent Nexys2 Board Reference Manual.
  http//www.digilentinc.com/Data/Products/NEXYS2/Ne
  xys2_rm.pdf
• FPGA Resources. Echelon Embedded.
  http//www.echelonembedded.com/fpgaresources/
• USB Protocol Specification. http//www.faculty.iu-
  bremen.de/birk/lectures/PC101-2003/14usb/FINAL20V
  ERSION/usb_protocol.html
• Universal Serial Bus. http//en.wikipedia.org/wiki
  /Usb

88
Questions?