USB2.0 Host Controller

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(No Transcript)
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USB2.0 Host Controller

• John S. Howard
• Staff EngineerIntel Architecture Labs
• Intel Corporation

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Agenda

• Project Overview
• Key Features Overview
• USB 2.0 Host Controller Architecture
• High-Speed Host Controller
• Interface Architecture
• Interface Data Structure Overview/Benefits
• Power Management
• Host Controller Compliance Program
• Summary

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Project Overview

• Enhanced Host Controller Specification for USB
• Defines the register (hardware/software)
  interfacefor a USB 2.0 capable host controller
• Revision 0.95 will be the first public release
• License agreement provides reciprocal royalty
  free license to manufacture compliant discrete
  USB 2.0 host controllers based on this
  specification

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Project Overview
Continued

• Revision 1.0 is the final specification
• License agreement provides reciprocal royalty
  free license to manufacture compliant USB 2.0
  host controllers based on this specification
• Intel developed specification with
  contributionsso far from
• NEC, Lucent, Philips, Compaq and Microsoft
• Licensees can also contribute to specification

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Project Overview

• Specification Development methodology
• Developed in parallel with USB 2.0 core
  specification
• Low-risk approach
• Leverage existing USB 1.1 HC implementations and
  knowledge base
• Provide solutions to well-known USB host
  controller problems
• Focus on reasonable hardware/software complexity
  tradeoffs
• Validate features whenever possible
• Built prototype driver and host controller in
  parallel with specification
• Host Controller Compliance Program
• Ensures host controllers are compliant to the
  specification

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USB 2.0 Host Controller Architecture

• Multi-function Controller delivers 3 port speeds
• Simplifies High-speed Host Controller
• Optimize for high-speed functionality
• Reuses USB 1.1 Host Controller Designs (drop-in)
• Allows port availability independent of presence
  ofhigh-speed capable software

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USB 2.0 Host Controller Architecture Port
Routing Rules

• Ports owned by Companion controllers when HS HC
  software is absent
• When HS HC Software is present, it configures
  High-Speed HC then
• Retains ownership for high-speed devices
• Releases individual port ownership if attached
  device is not high speed
• Routing Logic signals a disconnect on HS HC and a
  connect on Companion HC
• Ownership returns to HS HC on a disconnect event

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High-Speed Host Controller Interface Architecture

• Three-part Interface
• PCI Space
• Register Space
• Shared Memory Work Interface
• PCI Configuration Registers
• PCI Class Codes
• Memory space base addressfor register space
• Power Management Interface

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High-Speed Host Controller Interface Architecture

• Memory-based I/O Registers
• Capability Registers
• Implementation-specific,read-only parametersfor
  driver
• Operational Registers
• Host controller management
• List Management
• Port control registers

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High-Speed Host Controller Interface Architecture

• Shared Memory Work Lists
• Two schedule Lists (periodic, asynchronous)
• Queuing data structures
• Used for transfer types guarantee delivery
• Different data structures used for isochronous
• Different data structures for high- and
  full-speed
• Optimized for streaming isochronous data
• No support for retries

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High-Speed Host Controller Interface Architecture
(Overview)
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Shared Memory Work ListsQueuing Data Structure

• Queues are used for ALL Non-Isochronous transfers
• 1 queue per endpoint
• Each queue element (transaction
  descriptor)describes a buffer
• I.e. 1 to many transactions
• Up to 20 Kbytes per transaction descriptor
• 16Kbytes with worst-case buffer alignment
• No Hardware/software sync required to addwork to
  a queue
• Architecture optimized to provide
  efficientmemory accesses
• Block, burst accesses
• Reduced average number of memory accessesto
  start transaction

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Shared Memory Work ListsQueuing Data Structure
(Ex.)
Example Control Transfer Initial Condition QHD
empty
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Shared Memory Work ListsIsochronous Data
Structures

• Used only in periodic list
• Time-oriented data structure
• Frame number encoded in topology of list
• Position of work item in periodic list determines
  whenit will be seen and executed by the host
  controller
• No hardware (micro)-frame arithmetic required
• Different data structures for high-speedand
  low-speed
• High-speed data structure optimized for large
  transfers
• Full-speed data structure optimized
  forsplit-transaction support

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Shared Memory Work ListsHardware Scatter/Gather

• All transfer data structures arescatter/gather
  capable
• Simple hardware implementation
• No pointer arithmetic required
• Simple concatenation of page pointerto page
  offset to generate buffer address
• Software initializes page offset,
  hardwaremanages page pointers and page
  offsetbased on transfer progress

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Power Management

• High-speed controller power management
• USB port power management
• PCI Bus Power Management Interface
• Provides per/port capabilities for managing bus
  power as defined in USB specification
• Support defined for PCI Advanced Power management
  interface
• Compliant with PCI Bus Power Management Interface
  Specification, Revision 1.1

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USB 2.0 Host Controller Compliance Program

• Compliance testing includes
• Standard USB 2.0 Compliance tests
• Standard USB 2.0 Electrical tests
• Host controller-specific Interface Functional
  Testing
• Availability
• HC compliance test will be available from Intel
• Method of distribution (to be defined)
• Alpha-level tools available in Q3 2000
• Beta-level tools available in Q1 2001
• Production release available with release of 1.0
  hostcontroller specification

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USB 2.0 Host Controller Compliance Program

• HC-specific compliance software under
  development at Intel
• Special compliance devices(high-speed and
  full/low speed)
• Special-purpose application and driver for
  controlled testingand analysis
• Interface Functional Testing
• Device Interoperability
• USB 2.0 protocol andtransfer extensions
• System Interaction
• Etcetera,

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Summary

• Low-risk Introduction
• All ports are HS/FS/LS Capable
• Legacy (non-high-speed aware) software just works
• Re-use of 1.1 controllers simplifies high-speed
  controller
• Interface optimized for good memoryaccesses
  efficiency
• Reasonable tradeoff of hardware/software
  complexity

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Summary
Continued

• PCI power management compliant
• Host controller compliance program
• Revision 0.95 for discrete HC Q3 2000
• Gating item is validation of 2 discrete host
  controllers
• Revision 1.0 in 2001
• Gating item is validation of integrated host
  controller