Test Asynchronous FIR Filter Design

1
Test Asynchronous FIR Filter Design

• Presenter Po-Chun Hsieh
• AdvisorTzi-Dar Chiueh
• Date 2003/12/1

2
Outline

• Low Power Issue of Asynchronous Circuits
• Test FIR Design
• - Logic circuits
• - Multiplier
• - FIR Architecture
• Future work
• Conclusion
• Reference

3
Low Power Issue of Asynchronous Circuits

• No global clock
• Functions work only when needed
• Dynamic Logic and Domino Logic

4
Asynchronous FIR filter and other Asynchronous
Modules

• Every component of FIR works in each evaluation
• For other modules, functions work only when needed

5
Low power Filter

• Logic circuits
• Multiplier
• FIR Architecture

6
Computation Units

• 4-phase handshaking is easier to design
• Req in is low ? clean the content ? done is low
• Req in is high? evaluate? done is high

7
Dynamic Logic and Domino Logic

• Match the requirements for Computation Unit
• No spontaneous transitions, low power
• Drawbacks
• Must be Monotonous Inputs
• Completion Detection Methods

8
Problem of Bounded delay method

• How to design delay element ?

9
Problem of activity-monitoring completion-detectio
n (AMCD) method (1/2)

• Test the transitions at important points
• Used in Single-rail CMOS Logic

1
10
Problem of activity-monitoring completion-detectio
n (AMCD) method (2/2)

• When used in dynamic (domino) logic, maybe it
  will never pull down the signal

2
11
Differential Cascode Voltage Switch Logic (DCVSL)

• Dual-rail Domino Logic gate
• Drawbacks Area?Power consumption
• Completion detection method? only add in the
  output cascode stages

12
Low power Logic gate

• Single-rail bounded-delay dynamic (domino) logic
  gates are very low power, but have two problems
• Before finding solutions, choose to use DCVSL

13
Asynchronous Multiplier

• Multiplier is the most important part in a FIR
  filter
• Sign and Magnitude 5

14
Data Dependent Carry Save Adder Array (1/2)

• MD Multiplicand MR Multiplier PP Partial
  Product

3
15
Data Dependent Carry Save Adder Array (2/2)

• 4X4 Carry Save Adder array
• By probability, only turn on 50 adders

4
16
Partially work by DCVSL Logic

• If MR(n)1
• ( MR(n).t1 MR(n).f0 )
• then the adder cell works
• If MR(n)0
• ( MR(n).t0 MR(n).f1 )
• then the adder cell will not work

17
FIR Architecture

• H Handshake Circuit h(0)h(N) coefficients

18
Future Work

• Test the designed FIR module
• Search for low power FIR architecture and
  Multiplier
• Try to find solutions to the problems of
  single-rail dynamic (domino) logic

19
Conclusion

• Unlike other kinds of Asynchronous circuits,
  every component of FIR works every time.
• Choose FIR architecture, Multiplier, and
  Implement Circuits to make FIR low power.

20
Reference

• 1 Grass, E. and S. Jones, "Activity-monitoring
  completion-detection (AMCD) a new approach to
  achieve self-timing", Electronics Letters, vol.
  32, no. 2, pp. 86-88, January 1996
• 2 Bartlett, V.A. and E. Grass,
  "Completion-detection technique for dynamic
  logic," Electronics Letters, vol. 33, no. 22, pp.
  1850-1852, October 1997.
• 3 Bartlett, V. A. and E. Grass, A Self-Timed
  Multiplier using Condutional Evaluation", Proc.
  PATMOS'98, 8th International Workshop on Power,
  Timing, Modelling, Optimization and Simulation,
  Lyngby, Denmark, pp.429-438, October 1998
• 4 D.Kearney and N.W.Bergmnn, Bundled Data A
  syncheonous Multipliers with Data Dependent
  Computation Times,Proc. ASYNC97, 2nd Int.Symp.
  On Advanced Research in Asynchronous Circuits and
  Systems,pp. 186-197,1997
• 5 Bartlett, V. A. and E. Grass, A Low-Power
  Asynchronous VLSI FIR Filter", Proc. ARVLSI'01,
  19th Conference on Advanced Research in VLSI,
  Salt Lake City, Utah, USA, March 2001.