A Unified Approach to Fast Digital Processing for Beam Dampers, Instrumentation,

1
A Unified Approach toFast Digital Processing for
Beam Dampers, Instrumentation, Controls

• Bill Foster
• July 02

2
Whats the Scoop?

• 1) Fast, High Precision Pipelined ADCs
• AD6645 14 Bits, 105 MHz, SNR 72 dB
• AD9430 12 Bits, 210 MHz, SNR 65 dB
• 2) Fast , huge FPGAs
• e.g. Altera Stratix Apex devices
• Pre-built DSP blocks including 250 MHz digital
  filters
• gt 20 GMAC/s per chip
• 10 Mbits on-chip RAM, 1 Gbit/sec/pin digital I/O
• glueless LVDS interface to fast ADCs

3
Generic Hardware Concept for Accelerator
Instrumentation Control
53 MHz, TCLK, MDAT,...
Cables from Tunnel
INPUTS BPM Stripline Pickup Resistive
Wall Flying Wire PMT RF Fanback Kicker
Monitor etc.
FAST ADC
Monster FPGA
Minimal Analog Filter
CPU Bus VME/ VXI/ PCI/ PMC etc.
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. . .
. . .
. . .
FAST ADC
Minimal Analog Filter
OUTPUTS Stripline Kicker RF Fanout Analog
Monitor etc.
FAST DAC
4
Five Example Applications using this same basic
hardware

• 1) Universal Beam Position Monitors (BPMs)
• Handles full variety of FNAL beam RF structure
• 2) Generic instrumentation readout Scope
• ex Flying Wire readout for arbitrary bunches
• 3) Recycler / Injection Damper (fixed frequency)
• Bunch-by-bunch, narrow band, or both at once.
• Transverse and Longitudinal
• 4) Beam Loading Compensation
• 5) Universal Beam Dampers / Beamline Tuner

5
You can (basically) buy this...

• Prieto, Meyer et. al. evaluating 65MHz DDC for RR
  BPM upgrade
• Asmanskas, Foster purchasing 105 MHz version for
  RR Dampers

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Echotek ADC / DDC Board

• Board similar to this originated at SLAC
• Local users Prieto, Meyer, Voy Co.
• Digital Down Conversion Chip implements specific
  filtering algorithm (many parameters)
• Same chip used by Chase et. al. on board for
  e-cooling BPM with excellent results
• Echotek Board Includes medium-sized FPGA Output
  FIFO, (can bypass DDC chip)
• It is possible that we can do everything
  we need inside the FPGA, without DDC chip.

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AD6645 Functional Block Diagram

• Two-Stage Pipelined ADC
• Internal Track Hold
• Differential Analog Inputs

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Application 1 Universal BPM(Beam Position
Monitor)

• Measures position of each bunch on each pass
  around the ring with full-bandwidth FIR filter
• (R-L)/(RL) for each bunch measurement.
• Multi-bunch averages available for lower noise
• per batch, per turn, many turns, different
  bandwidths
• Multiple users can share hardware w/o conflicts
• ADC is always active, FPGA stores data many ways
• Same Hardware OK for Booster, MI, RR, TeV,
  beamlines.

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Universal BPM Hardware
53 MHz, TCLK, MDAT,...
106 MHz
Split Plate Pickup 1
Monster FPGA(s)
Minimal Analog Filter
ADC
R
14
Minimal Analog Filter
CPU Bus VME/ VXI/ PCI/ PMC etc.
ADC
L
. . .
. . .
Pickup 4
Minimal Analog Filter
ADC
T
Minimal Analog Filter
B
ADC
FAST DAC
Analog Position Monitor Test Point (Optional)
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Appropriate Digital Filtering can deal with all
these Bunch RF Structures
14
Universal BPM Application Signal Processing
Steps

• 1) Bandwidth-Limit input signal to 53 MHz
• 2) 14 Bit Digitization at 106 MHz / 212 MHz
• 3) FIR filter(s) to get single-bunch signal(s)
• 4) Sum Difference of plate signals
• 5) (Difference / Sum) gives position
• 6) Linearization lookup table or polynomials
• 7) Bunch, Batch, Multiturn Averaging
• 8) Scope Trace Buffers on every signal
• Multiple users can be acquiring and filtering
  data multiple ways without conflicts

Echotek Board
Inside FPGA
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Universal BPM Signal Processing Step 1
Bandwidth Limit Signal

• Raw signal has high-frequency components which
  can cause signal to be missed by ADC
• Aliasing
• Bandwidth limited signal (to 53 MHz) cannot be
  missed by 106 MHz ADC
• Example Gaussian Filter
• Eliminate low-frequency ripple, baseline shifts,
  etc. with Transformer or AC coupling
• Digital Filtering can provide additional
  rejection

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BPM Signal Doublet
This signal is too fast - can be missed by 100
MHz ADC

• Positive signal as image charge arrives, negative
  as it leaves gt Bipolar Doublet

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Signal From Long Stripline

• If Stripline Length gt Beam Pulse Length,
• we get two separate opposite-polarity pulses

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If Beam Pulselength gt Pickup Length
This type of signal sets low end of Dynamic
Range

• Shape is the derivative of the beam current.
• Pulse height is reduced VOUT 1/(FWHM)2

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Gaussian Filter - Impulse Response
Spreads signal /-5ns in time so it will not be
missed by ADC
Reduces ADC Dynamic Range requirement, since
spike does not have to be digitized

• Many implementations, e.g. traversal filter

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Gaussian Filter - Doublet Response
Filtered Output Pulse Shape is insensitive to
Bunch Length (for Tb lt 10ns)
Filtered Signal can be sampled by 100 MHz ADC
Digitized Pulsehight is A - B
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Gaussian Filter - Pulse Train Response
Filter Output is good sine wave independent of
bunch length
A - B still gives good bunch-by-bunch
measurement
Can digitally average over many bunches in a
batch to get lower noise
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Analog Filter Design is Complicated!

• Tradeoffs between sharpness of frequency cutoff
  and propagation delay spread
• Gaussian filter chosen here for no good reason
• Echotek board uses hybrid lowpass filter module
  from Mini-circuits. Is this what we want?

Cutoff is Sharper than Gaussian
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Universal BPM Signal Processing Step 2
Analog-Digital Conversion

• What ADC Clock Speed is needed?
• 53 MHz Bandwidth limited signal, sampled by 106
  MHz ADC, measures either in-phase (cosine) or
  quadrature (sine) component
• but not both gt ADC clock phasing matters!
• 212 MHz sampling measures both in-phase and
  quadrature components. Phasing is not critical
  to determine vector magnitude.

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In-Phase and Quadrature Sampling
A - B gives bunch-by-bunch in-phase signal
D - (CE)/2 gives bunch-by-bunch
out-of-phase quadrature signal
Vector Sum sqrt(I2 Q2) is insensitive to
clock jitter

• This is the argument for sampling at 2x Nyquist

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This ADC can sample 53 MHz signals at 4 samples
per cycle to measure both In-Phase and Quadrature
on each cycle
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Synchronous vs. Asynchronous ADC Sampling

• The choice is between N53 MHz beam phase locked
  sampling, or asynchronous sampling at a
  (possibly) lower rate
• Asynchronous sampling of a waveform will allow
  you to recover all the information, IF
• you know that the input is a pure sine wave, or
• you know the input is repetitive (stored beam),
  or
• the sampling rate is much higher than fMAX

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The Perils of Undersamplinga Single-Pass Beam
If a single-pass beam does not have uniform bunch
populations, the ADC input is NOT a good sine
wave and an undersampled waveform can give an
erroneous picture of the beam signal.
The signal CAN be reconstructed with many passes
of stored beam.
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Conclusions on ADC Clock Rate

• A Universal BPM system must sample at 2-4x
  the maximum bunch frequency, depending on whether
  we want to guarantee the clock phase stays
  aligned or not.
• You can never be
• too rich
• too thin
• or have too many ADC samples

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Universal BPM Signal Processing How Many ADC
bits are needed?

• Biggest Signal Coalesced Proton Bunch
• 350E9 particles in single 10ns bunch
• if bunch is shorter, doesnt matter, filter will
  spread it
• Smallest Signal Antiproton Pilot Shot at 2.5
  MHz
• 10E9 particles/bunch in four 50ns bunches
• this gives 25x smaller pulse height than same
  number of particles in 10ns bunch, but 5x
  smaller pulse area
• Off-center beam positions require an additional
  41 dynamic range (maybe less with hybrid)

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Biggest Signal in Main Injector
Coalesced bunch puts 350E9 in single 53MHz
Bucket
Bunch length will be 3ns at transition with GPJ
low emittance coalescing.
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No guarantees on bunch populations or
individual bunch transverse positions
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ADC Dynamic Range(Main Injector, which is worst
case)

• Set up so 14 Bit ADC (16k counts) almost
  saturates for full scale hit from coalesced bunch
  (300E9)
• Lose factor of 30 (10E9/300E9) for bunch charge
  of Antiproton Pilot Shot
• Lose Factor of 25 for pulse height of 50ns bunch
  vs. 10ns bunch gt 21 counts per sample
• Signal from 4-bunch pilot shot shows up in 40
  samples gt800 counts if beam centered in BPM
• ADC bit noise is sub-mm contribution to
  resolution

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Universal BPM Signal Processing Step 3
Digital Filter

• Many Filters can operate in parallel in FPGA
• single Bunch FIR filter (weighted sum of samples)
• single Batch filter (53 MHz, 2.5 MHz, 7.5 Mhz)
• Multi-pass averaging (can extract all harmonics
  of revolution frequency for stored beam)
• Automatic peak-finding or calculation of
  I2Q2 to make timing less critical
• Waveform capture allows filters to be debugged
  optimized new versions tested offline

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Universal BPM Signal Processing Step 4,5,6
Beam Position Signal

• 4) Calculate Sum Difference of plate signals
• Traditionally done in analog S-? Hybrid
• This saves 1-3 bits of dynamic range for ADC
• 14-bit ADC dynamic range OK without Hybrid
• 5) (Difference / Sum) gives position
• X (Right - Left) / (Right Left)
• 6) Linearization lookup table or
  polynomials (X,Y) CALIBRATED F(XRAW, YRAW)

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Main Injector BPM Response Map
J. Crisp

• Linearization can be done in FPGA or readout
  software

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Universal BPM Signal Processing Step 7
Averaging and Filtering

• Many Types of averaging possible
• Position Averaging over Bunches in a Batch
• Multi-Turn Averaging of Positions
• Multi-turn averaging of Raw Signals
• Fitting to betatron frequency (injection errors)
• - this gives info for ?-function measurement
• Emulation of DDC chip functions
• Spectrum analysis of position phase
• Different filters can be simultaneously active

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Application 2 Generic Instrumentation Readout
Scope

• What we want in a Generic Scope
• 1) Ability to trigger on TCLK events, Beam Synch
  Events, analog threshold crossings of different
  channels, etc.
• 2) Multiple Users Sharing without conflicts
• - separate copies of trigger logic
• - separate buffers to store captured signals
• - separate filter algorithms run simultaneously
• 3) Common hardware software among systems

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Example Application of Generic Scope Flying
Wire PMT Readout
53 MHz, TCLK, MDAT,...
PMT(s) in Tunnel
106 MHz
FAST ADC
Monster FPGA
Minimal Analog Filter
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FAST ADC
Minimal Analog Filter
CPU Bus VME/ VXI/ PCI/ PMC etc.
FAST ADC
Minimal Analog Filter
Encoder Signals
FAST ADC
Minimal Analog Filter
Motor Drive
Motor
DAC
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Example Application of Generic Scope Flying
Wire PMT Readout

• Photomultiplier Tube (PMT) pulses presented to
  Analog filter to limit BW
• Summing circuits in FPGA give total PMT pulse
  height in narrow and wide gates
• Individual gates report signals for 36x36 or more
  bunches, average over many turns, etc.
• FPGA can be used to control trigger the fly
• Raw PMT pulses can be simultaneously looked at
  via multi-user hooks

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Application 3 Recycler / Injection Damper

• Fixed revolution frequency simplifies design.
• Measures position of each bunch on each pass,
  then kicks it back on center.
• Same circuit usable for Injection Dampers, which
  also operate at fixed frequency.
• Digital multi-turn filters used to calculate
  kick.
• Narrow-band and Broad-band filters can run
  simultaneously on same device, if needed.

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Analog Beam Damper SystemSimplified schematic of
narrow band Transverse Damper for 53 MHz bunched
beam
McGinnis
?-?
Power Amp (Buy / Exists)
Move from Analog to Digital Processing inside
FPGA

• The Digital system can exactly emulate this,
  plus run other algorithms for various bunch
  structures.

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Recycler / Injection Damper(same generic
hardware)
53 MHz, TCLK, MDAT,...
106 MHz
Stripline Pickup A
FAST ADC
Monster FPGA
Minimal Analog Filter
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FAST ADC
Minimal Analog Filter
CPU Bus VME/ VXI/ PCI/ PMC etc.
FAST ADC
OPTIONAL Pickup B
Minimal Analog Filter
FAST ADC
Minimal Analog Filter
Power Amp.
Stripline Kicker
106 MHz
FAST DAC
gt 27 MHz
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Emulating a 53 MHz Analog Mixer /LPF
ANALOG MIXER FILTER
Impulse response
53 MHz sin
70 MHz LPF
BPM
LPF
53 MHz DIGITAL FILTER (FIR or IIR)
Impulse response
53 MHz Clock
70 MHz LPF
Digital Filter
BPM
ADC

• Both circuits have identical impulse response,
• and identical sensitivity to 53 MHz clock noise

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Advantages of Digital Filters

• Digital filter can also operate at multiple lower
  frequencies ...simultaneously if desired.
• MI will not be blind at 2.5 and 7.5 MHz Beam
• Digital filters more reproducible (gtspares!)
• Re-use Standard hardware with new FPGA code
• or same code with different filter coefficients
• Inputs and Outputs clearly defined
• filters can be developed debugged offline

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Signal Processing Steps forRecycler / Injection
Damper

• 1) Bandwidth-Limit input signal to 53 MHz
• 2) 14 Bit Digitization at 106 MHz or 212 MHz
• 3) Filter to get single-bunch signal
• 4) Sum Difference of BPM plate signals
• 5) Multi turn orbit difference filter w/delay
• 6) Pickup Mixing for correct Betatron Phase
• 7) Pre-Emphasis for Kicker Amp Cable
• 8) Power Amp for Kicker

Echotek Board
Inside FPGA
Buy
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Processing Beam Position Measurements to
Calculate Kick

• One or two beam pickups
• One or many turns
• Nasty problems
• kicker phase adjustments vs. machine tune
• DC orbit offset rejection

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3 - Turn Filter
Arbitrary Betatron Phase of Kicker can be
accommodated

• Damper kick is calculated from single BPM
  position reading on 3 successive turns.

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HERA-P Damper uses a 3-turn Digital FIR Filter
Klute, Kohaupt et. al. EPAC 96

• Digital Bunch by Bunch _at_ 96ns Spacing
• Immediate digitization following peak detection
• a very attractive system for FNAL to copy...

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Recycler / Injection Damper FPGA Logic(single
pickup with 3-turn filter)
Gain Balance
Weighted Sum for Arbitrary Betatron Phase
Pickup
ADC
FIR Filter
1-turn Delay
1-turn Delay
1-turn Delay
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ADC
Standard BPM Processing
3 - Turn Filter
Power Amp.
Stripline Kicker
106 MHz
Optional Pre-compensation Filter for Cable
DAC
gt 27 MHz
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3 Turn Filter Coefficients

• Damper kick is weighted sum of beam positions on
  the 3 previous turns.
• 3 Filter Coefficients Uniquely Determined by
• System Gain
• Betatron Phase Desired at Kicker
• Constraint that sum of filter coefficients 0
  (so that filter does not respond to DC
  offsets.)

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2 Turn Filter (2 pickups)
Arbitrary Betatron Phase of Kicker can be
accommodated using both BPMs

• Damper kick is calculated from 2 BPM position
  readings on two successive turns.

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Recycler / Injection Damper FPGA Logic(two
pickups with 2-turn filter)
GAIN
Pickup 1
ADC
FIR Filter
14
ADC
Weighted Sum for Arbitrary Betatron Phase
1-turn Delay
1-turn Delay
GAIN
Pickup 2
ADC
FIR Filter
14
2 - Turn Filter
ADC
Power Amp.
Stripline Kicker
106 MHz
Optional Precompensation Filter for Cable
DAC
gt 27 MHz
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Two-Turn Filter Coefficients

• First step synthesizes desired Betatron phase at
  kicker from linear combination of signals from
  two different pickups.
• Final step is to take orbit difference on two
  successive turns. Unweighted subtraction
  ensures zero response to DC offsets.
• Coefficients in registers writeable from CPU

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Narrow band vs. Wide band Dampers

• In some cases instabilities only occur with
  specific frequency and mode patterns in ring
• Dealing specifically with those modes lowers the
  required kicker power and reduces noise.
• A wide band (bunch-by-bunch) damper can use
  digital filtering to provide higher gain for
  specific mode patterns.
• Many digital filters can operate simultaneously
  inside some device -- ADC and DAC are shared

The flexibility of Digital Filtering inside the
FPGA is a major advantage of this approach.
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Damper Output Filter

• Multiple Filters in parallel calculate kick
• Kick signal is split according to frequency
• Hi-bandwidth outputs to stripline kicker
• cable amplifier pre-compensation w/FIR
• Low bandwidth outputs to magnetic kicker (used
  mainly at injection)

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Application 4 Beam Loading Compensation

• 1) Digital Pipeline to reproduce IQ signals from
  RW bunch monitor with N-turn delay. (N1...1/?S)
• 2) Digital filters for transients and synchrotron
  osc.
• Input Resistive-wall monitor ( RF gap
  monitor?)
• Digitization bunch-by-bunch I Q signals
• Outputs IQ to damper cavity, or LLRF
• frequency swing issues for LLRF drive
• Antiproton vs. Proton timing

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Longitudinal Beam Instability in FMI

• Occurs with 7 bunches filled (out of 588)
• Prevents low emittance bunch coalescing

First Bunch OK
7th Bunch Trashed

• Driven by cavity wake fields within bunch train
• This is a time domain problem!

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Time Domain vs. Frequency Domain

• The classical mode analysis applies best to
  completely filled machines with instabilities
  which develop over full circumference.
• Many of the problems FNAL sees are transient
  (time domain) phenomena (e.g. last slide).
• High bandwidth digital processing is equally
  comfortable with both, simultaneously.
• Example damping instability on previous slide
• 1) Wake field subtraction with narrowband filter.
  
• 2) Bunch-by-bunch feedback.
• all on same FPGA.

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2.5 MHz Beam Loading in MI
Gerry Jackson

• 7-Bunch train causes cavity to ring
• Feedback kills ringing before next turn
• Need feed-forward to kill effects within train

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Frequency Sweep Issues

• Machines with frequency sweep (?Booster!) must
  adjust ADC input clock and DAC output clock
  phases as frequency sweeps.
• This can be generated with Phase-locked loops and
  delay-locked loops present inside FPGAs.
• This requires access to both the RF clock, and
  a cable-delayed version of the RF
  clock, as timing references.
• One-turn digital delay using FIFOs in FPGAs.
• Same hardware can be used for Booster thru
  Tevatron.

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RF Clockingwith acceleration
Equal Length Cable Fanout so Beam Sees Same RF
Phase at all Cavities as RF Frequency Sweeps
During Acceleration
of Clock Cycles per Turn is harmonic number h
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ADC Clockingduring frequency sweep
Round-Trip Cable Delay on ADC Clock ensures ADC
Clock Beam Input Stay in Phase as Beam
Accelerates
May need additional phase adjustment to track
phase jumps at transition, etc.
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DAC Clockingduring frequency sweep
Propagation Delay CK ? DAC ? Cable ?
Kicker should match RF Fanout Delay so Kick Stays
in Phase as Beam Accelerates
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Generic Dampertolerating frequency sweep
All Logic Inside FPGA
FIFO needed due to phase shifts between DAC and
ADC clocks as beam accelerates
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DAC Issues

• Bunch-by-bunch (transverse) kicker
• step function with flat-top after cable at kicker
• FIR filter can pre-compensate for Amp Cable
• RF drive
• heavily modulated 53 MHz sine wave
• High Bandwidth DACs now include interpolation
  logic to make up missing points on sine wave
• yields higher effective update rate 400 MHz

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AD9777 TxDAC
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Application 5 Universal Damper

• Big advantage if same Damper hardware can be used
  for Booster, RR, MI, TeV
• Frequency swing during acceleration introduces
  same timing complications as above.
• Digital Filter which operates on I Q signals
  from individual 53 MHz bunches can also be
  reprogrammed to operate at lower frequencies.
• Tevatron noise requirements make all dampers
  tough (except injection dampers).

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Universal Damper Application
Cable Delayed 53 MHz Clock
53 MHz, TCLK, MDAT,...
106 MHz
Stripline Pickup A
FAST ADC
Monster FPGA
Minimal Analog Filter
14
FAST ADC
Minimal Analog Filter
CPU Bus VME/ VXI/ PCI/ PMC etc.
Stripline Pickup B
FAST ADC
Minimal Analog Filter
FAST ADC
Minimal Analog Filter
Power Amp.
Stripline Kicker
106 MHz
FAST DAC
gt 27 MHz
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Universal-Damper Application Signal
Processing Steps

• 1) Bandwidth-Limit input signal to 53 MHz
• 2) 14 Bit Digitization at 106 MHz or 212 MHz
• 3) FIR filter to get single-bunch signal
• 4) Sum Difference of plate signals
• 5) Multi turn difference filter (FIR) w/delay
• 6) Pickup Mixing for correct Betatron Phase
• 7) Bunch-by-bunch gain, dead band etc.
• 8) Timing Corrections for Frequency Sweep
• 9) Pre-Emphasis for Kicker Power Amp
• 10) Power Amp for Kicker

Echotek Board
Inside FPGA
Buy
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Damper Parameters for various Machines at FNAL

• (See Doc.)

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CONCLUSIONS

• Fast ADCs and Huge FPGAs may revolutionize
  Accelerator Instrumentation
• The same basic hardware can perform a large
  number of Instrumentation Control functions
• A good first application of this technology is
  a Universal beam damper

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- To Pursue This -

• Capture digitized waveforms of relevant signals
• to begin development of analog and digital
  filters
• Test fitting example logic into FPGAs
• Contemplate a change in balance of skills
• fewer custom analog designs, NIM modules, etc.
• fewer designs, more complex FPGA programming.
• Need to train large body of expertise ASAP
• Standardize hardware No orphaned digital
  projects!
• Train many people on standardized components.
• Identify expertise at lab, experiments, and
  elsewhere.