Logic Synthesis

1
Logic Synthesis

• Timing Optimization

2
Restructuring for Timing Optimization

• Outline
• Definitions and problem statement
• Overview of techniques (motivated by adders)
• Tree height reduction (THR)
• Generalized bypass transform (GBX)
• Generalized select transform (GST)
• Partial collapsing

3
Timing Optimization

• Factors determining delay of circuit
• Underlying circuit technology
• Circuit type (e.g. domino, static CMOS, etc.)
• Gate type
• Gate size
• Logical structure of circuit
• Length of computation paths
• False paths
• Buffering
• Parasitics
• Wire loads
• Layout

4
Problem Statement

• Given
• Initial circuit function description
• Library of primitive functions
• Performance constraints (arrival/required times)
• Generate
• an implementation of the circuit using the
  primitive functions, such that
• performance constraints are met
• circuit area is minimized

5
Current Design Process
Behavioral description
Behavior Optimization (scheduling)
Logic and latches
Partitioning (retiming)
Logic equations

• Logic synthesis
• Technology independent
• Technology mapping

• Gate library
• Perf. Constraints
• Delay models

Gate netlist
Timing driven place and route
Layout
6
Technology Mapping for Delay
Function tree
Buffer tree
7
Overview of Solutions for Delay

• Circuit re-structuring
• Rescheduling operations to reduce time of
  computation
• Implementation of function trees (technology
  mapping)
• Selection of gates from library
• Minimum delay (load independent model - Kukimoto)
• Minimize delay and area (Jongeneel, DAC00)
• (combines Lehman-Watanabe and Kukimoto)
• Implementation of buffer trees
• Touati (LT-trees)
• Singh
• Resizing
• Constant delay synthesis

8
Circuit Restructuring

• Approaches
• Local
• Mimic optimization techniques in adders
• Carry lookahead (THR tree height reduction)
• Conditional sum (GST transformation)
• Carry bypass (GBX transformation)
• Global
• Reduce depth of entire circuit
• Partial collapsing
• Boolean simplification

9
Restructuring Methods

• Performance measured by
• levels,
• sensitizable paths,
• technology dependent delays
• Level based optimizations
• Tree height reduction (Singh 88)
• Partial collapsing and simplification (Touati
  91)
• Generalized select transform (Berman 90)
• Sensitizable paths
• Generalized bypass transform (McGeer 91)

10
Tree-Height Reduction (THR)
Singh88
6
n
Collapsed Critical region
5
n
Critical region
5
5
Duplicated logic
1
l
m
m
1
1
1
4
1
k
4
2
k
0
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j
i
j
3
3
h
h
0
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2
a
b
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11
Tree-Height Reduction
4
New delay 5
n
3
n
Collapsed Critical region
5
5
2
Duplicated logic
1
m
m
1
1
1
1
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1
4
2
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k
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0
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12
Generalized bypass transform (GBX)

• Make critical path false
• Speed up the circuit
• Bypass logic of critical path(s)

McGeer91
fmf

fm1
fng
fm f

fm1
fng
0
g
1
dg __ df
Boolean difference
s-a-0 redundant
13
GBX and KMS transform

• GBX gives little area increase, BUT creates an
  untestable fault
• (on control input to multiplexer)
• KMS transform (remove false paths without
  increasing delay)
• fk is last node on false path that fans out.
• Duplicate false path f1,, fk -gt f1, , fk
• fj fans out to every fanout of fj except fj1,
  and fj just fans out to fj1
• Set f0 input to f1 to controlling value and
  propagate constant (can do because path is false
  and does not fanout)
• KMS results
• Function of every node, except f1, ,fk is
  unchanged
• Added k nodes
• Area added in linear in size of length of false
  paths in practice small area increase.

14
KMS
Keutzer, Malik, Saldanha90
fm1
fmk1
fm2
fn
fmk

Delay is not increased
fm1
fm2
fmk

fm1
fmk1
fm2
fn
fmk

0
15
Generalized select transform (GST)

• Berman90 Late signal feeds multiplexor

a
out
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a0
0
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out
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a1
1
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16
GST vs GBX
a
c
g
h
0

g
b
1
a
GBX
a
c
dh __ da
g
GBX
h
0

g
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1
a
a0
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a1
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a0
out
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GST
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a
17
GST vs GBX

• Select transform appears to be more area
  efficient
• But Boolean difference generally more efficiently
  formed in practice
• No delay/speedup advantage for either transform
• Can reuse parts of the critical paths for
  multiple fanouts on GST

out2
GST
0
1
a
out1
0
a0
b
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d
e
f
g
1
a1
b
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a
18
Technology Independent Delay Reductions

• Generally THR, GBX, GST (critical path based
  methods) work OK,
• but very greedy and computationally expensive
• Why are technology independent delay reductions
  hard?
• Lack of fast and accurate delay models
• levels, fast but crude
• levels correction term (fanout, wires, ) a
  little better, but still crude (what coefficients
  to use?)
• Technology mapped reasonable, but very slow
• Place and route better but extremely slow
• Silicon best, but infeasibly slow (except for
  FPGAs)

s l o w e r
b e t t e r
19
Conclusions

• Variety of methods for delay optimization
• No single technique dominates
• When applied to ripple-carry adder get
• Carry-lookahead adder (THR)
• Carry-bypass adder (GBX)
• Carry-select adder (GST)
• Clustering/Partial collapse
• All techniques ignore false paths when assessing
  the delay and critical regions
• Can use KMS transform to eliminate false paths
  without increasing delay (Caveat potentially
  large increase in area)