Lab 2 Basic Gates in a PLD

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Lab 2Basic Gates in a PLD

• Module M2.3
• Section 4.2
• Experiment 2 (p. 63)

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Experiment 2
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(No Transcript)
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CUPL Header
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CUPL Comments
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CUPL Inputs and Outputs
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CUPL Logic Equations
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CUPL Chip Diagramin .DOC File
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Fuse Plot for !X
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Structure of the GAL 16V8 PLD
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Fuse Plot for !Y
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Structure of the GAL 16V8 PLD
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Fuse Plot for X Y
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Structure of the GAL 16V8 PLD
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Fuse Plot for !(X Y)
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GAL 16V8 Polarity Control
OE
A
C
Pin
B
Polarity
X
X
closed B 0 C A

open B 1

C !A
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Fuse Plot for X Y
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Fuse Plot for !(X Y)
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Fuse Plot for X Y
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Structure of the GAL 16V8 PLD
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Fuse Plot for !(X Y)
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Fuse Plot for X Y
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Structure of the GAL 16V8 PLD
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Fuse Plot for !(X Y)
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JEDEC File
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JEDEC File Header
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JEDEC File Fuse Map
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Experiment 2Basic Gates

• Modify the file, Exp2.pld, by using pins 6 and 7
  for the two inputs X and Y respectively.
• Modify the simulation file, Exp2.si on the web to
  use your header.
• Compile the program using WinCupl and run the
  simulation.
• Print out the chip diagram from the .DOC file.
• Print out the fuse maps.
• Program the GAL 16V8 chip.

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Experiment 2Basic Gates

• Connect pins 6 (X) and 7 (Y) to Out1 and Out0.
• Connect pins 12-15 to In4-In1. Print the truth
  table. Label each output column with the
  appropriate gate.
• Connect pins 16-19 to In4-In1. Print the truth
  table. Label each output column with the
  appropriate gate.
• Explain the fuse maps.