Title: Enabling Technologies for Reconfigurable Computing Part 4: FPGAs: recent developments Wednesday, November 21, 16.00
1Enabling Technologies for Reconfigurable
Computing Part 4FPGAs recent developments
Wednesday, November 21, 16.00 17.30 hrs.
November 21, 2001, Tampere, Finland
- Reiner Hartenstein
- University of
- Kaiserslautern
2Schedule
time slot
08.30 10.00 Reconfigurable Computing (RC)
10.00 10.30 coffee break
10.30 12.00 Stream-based Computing for RC
12.00 14.00 lunch break
14.00 15.30 Resources for RC
15.30 16.00 coffee break
16.00 17.30 FPGAs recent developments
3gtgt Configware Market
- Configware Market
- FPGA Market
- Embedded Systems (Co-Design)
- Hardwired IP Cores on Board
- Run-Time Reconfiguration (RTR)
- Rapid Prototyping ASIC Emulation
- Evolvable Hardware (EH)
- Academic Expertise
- ASICs dead
- Soft CPU
- HLLs
- Problems to be solved
4Configware heading for mainstream
- Configware market taking off for mainstream
- FPGA-based designs more complex, even SoC
- No design productivity and quality without good
configware libraries (soft IP cores) from various
application areas. - Growing no. of independent configware houses
(soft IP core vendors) and design services - AllianceCORE Reference Design Alliance
- Currently the top FPGA vendors are the key
innovators and meet most configware demand.
5bleeding edge designs
- Infinite amount of gates not yet available on a
chip - 3 mio gates (10 mio in 2003 ?) far away from
"infinite" - Bleeding edge designs only with sophisticated EDA
tools - Excessive optimization needed
- Hardware epertise is inevitable for the designer.
- improve and simplify the design flow the user
- provide rich configware libraries of soft IP
cores, - control appl., networking, wireless
telecommunication, data communication, embedded
and consumer markets.
6Configware (soft IP Products)
- For libraries, creation and reuse of configware
- To search for IPs see List of all available IP
- The AllianceCORE program is a cooperation between
Xilinx and third-party core developers - The Xilinx Reference Design Alliance Program
- The Xilinx University Program
- LogiCORE soft IP with LogiCORE PCI Interface.
- Consultants
7EDA as the Key Enabler (major EDA vendors)
- Select EDA quality / productivity, not FPGA
architectures - EDA often has massive software quality problems
- Customer highest priority EDA center of
excellence - collecting EDA expertise and EDA user experience
- to assemble best possible tool environments
- for optimum support design teams
- to cope with interoperability problems
- to keep track with the EDA scene as a rapidly
moving target - being fabless, FPGA vendors spend most qualified
manpower in development of EDA, IP cores,
applications , support - Xilinx and Altera are morphing into EDA
companies.
8OS for FPGAs
- separate EDA software market, comparable to the
compiler / OS market in computers, - Cadence, Mentor, Synopsys just jumped in.
- lt 5 Xilinx / Altera income from EDA SW
- Changing EDA Tools Market
- Major configware EDA vendors
- Altera
- Cadence
- Mentor Graphics
- Synopsys
- Xilinx
9EDA Software for Xilinx
- Full design flow from Cadence, Mentor, Synopsys
- Xilinx Software AllianceEDA Program
- Alliance Series Development System.
- Foundation Series Development Systems.
- Xilinx Foundation Series ISE (Integrated
Synthesis Environment) - free WebPOWERED SW w. WebFitter WebPACK-ISE
- StateCAD XE and HDL Bencher
- Foundation Base Express
- Foundation ISE Base Express
10Foundation ISE Base Express
- ModelSim Xilinx Edition (ModelSim XE)
- Forge Compiler
- Modular Design
- Chipscope ILA
- The Xilinx System Generator
- XPower
- JBits SDK
- The Xilinx XtremeDSP Initiative
- MathWorks / Xilinx Alliance
- System Generator
- Wind River / Xilinx alliance
11Altera EDA
- Altera was founded in June 1983
- EDA synthesis, place route, and, verification
- Quartus II APEX, Excalibur, Mercury, FLEX 6000
families - MAXPLUS II FLEX, ACEX MAX families
- Flow with Quartus II Mentor Graphics, Synopsys,
Synplicity deliver a design design software to
support Altera SOPC solutions. - Mentor only EDA vendor w. complete design
environment f. APEX II incl. IP, design capture,
simulation, synthesis, and h/s co-verification - Configware Altera offers over a hundred IP cores
- Third party IP core design services and
consultants
12Cadence
- FPGA Designer top-down FPGA design system,
- high-level mapping, architecture-specific
optimization, - Verilog,VHDL, schematic-level design entry.
- Verilog, VHDL to Synergy (logic synthesis) and
FPGA Designer - FPGAs simulated by themselves using Cadence's
Verilog-XL or Leapfrog VHDL simulators and - simulated w. rest of the system design w. Logic
Workbench board/system verification envment. - Libraries for the leading FPGA manufacturers.
13Mentor Graphics
- System Design and Verification.
- PCB design and analysis
- IC Design and Verification
- shifts ASIC design flow to FPGAs (Altera, Xilinx)
- by FPGA Advantage with IP support
- by ModuleWare,
- Xilinx CORE Generator
- Altera MegaWizard integration,
14Synopsys
- FPGA Compiler II
- Version of ASIC Design Compiler Ultra
- Block Level Incremental Synthesis (BLIS)
- ASIC lt-gt FPGA migration
- Actel, Altera, Atmel, Cypress, Lattice, Lucent,
Quicklogic, Triscend, Xilinx
15gtgt FPGA Market
- Configware Market
- FPGA Market
- Embedded Systems (Co-Design)
- Hardwired IP Cores on Board
- Run-Time Reconfiguration (RTR)
- Rapid Prototyping ASIC Emulation
- Evolvable Hardware (EH)
- Academic Expertise
- ASICs dead
- Soft CPU
- HLLs
- Problems to be solved
16Top 4 PLD Manufacturers 2000
17FPGA market 1998 / 1999
Source IC Insights Inc. Meanwhile, Xilinx
acquired Philips' MOS PLD
business, Lattice purchased Vantis. .
18.... into every application
- Dataquest PLD market gt 7 billion by 2003.
- fastest growing segment of semiconductor
market. - IP reuse and "pre-fabricated" components for the
efficiency of design and use for PLDs - FPGAs are going into every type of application.
19.... going into every type of applicationGordon
Bell
20Xilinx
- fabless FPGA semi vendor, San Jose, Ca, founded
1984 - key patents on FPGAs (expiring in a few years)
- Fortune 2001 No. 14 Best Company to work for in
(intel no. 42, hp no. 64, TI no. 65). - DARPA grant (Nov99) to develop Jbits API tools
for internet reconfigurable / upgradable logic
(w. VT) - Less brilliant early/mid 90ies (president Curt
Wozniak) 1995 market share from 84 down to 62
Dataquest - As designs get larger, Xilinx losed its advantage
(bugfixes did not require to burn new chips) - meanwhile, weeks of expensive debug time needed
21Xilinx Flexware
- Virtex, Virtex-II, first w. 1 mio system gates.
- Virtex-E series gt 3 mio system gates.
- Virtex-EM on a copper process addit. on chip
memory f. network switch appl. - The Virtex XCV3200E gt 3 million gates,
0.15-micron technology, - Spartan, Spartan-XL, Spartan-II
- for low-cost, high volume applications as ASIC
replacements - Multiple I/O standards, on-chip block RAM,
digital delay lock loops - eliminate phase lock loops, FIFOs, I/O xlators ,
system bus drivers - XC4000XV, XC4000XL/XLA, CPLD low-cost families
- rapid development, longer system life, robust
field upgradability - support In-System Programming (ISP), in-board
debugging, - test during manufacturing, field upgrades, full
JTAG compliant interface - CoolRunner low power, high speed/density,
standby mode. - Military Aerospace QPRO high-reliability QML
certified - Configuration Storage Devices
22Altera Flexware
- Newer families APEX 20KE, APEX 20KC, APEX II,
MAX 7000B, ACEX 1K, Excalibur, Mercury families. - Apex EP20K1500E (0.18-µ), up to 2.4 mio system
gates, - APEX II (all-copper 0.13-µ) f. data path
applications, supports many I/O standards. 1-Gbps
True-LVDS performance - wQ2001, an ARM-based Excalibur device
- Altera mainstream MAX 7000A, 3000A FLEX 6000,
10KA, 10KE APEX 20K families. - Mature and other Classic, MAX 7000, 7000S,
9000 FLEX 8000, 10K families.
23Triscend CSoC
Kean
24gtgt Embedded Systems (Co-Design)
- Configware Market
- FPGA Market
- Embedded Systems (Co-Design)
- Hardwired IP Cores on Board
- Run-Time Reconfiguration (RTR)
- Rapid Prototyping ASIC Emulation
- Evolvable Hardware (EH)
- Academic Expertise
- ASICs dead
- Soft CPU
- HLLs
- Problems to be solved
25Goal away from complex design flow
à la S. Guccione
26Overcome traditional separate design flow
à la S. Guccione
27Overcome traditional co-processing design
separate flow -gt JBits Design Flow
à la S. Guccione
28Embedded hardw. CPU memory cores on chip.
à la S. Guccione
29new directions in application development
- new directions in application development.
- aut. partitioning compilers designer
productivity - like CoDe-X (Jürgen Becker, Univ. of Karlsruhe),
- supports Run-Time Reconfiguration (RTR), a key
enabler of error handling and fault correction by
partial re-routing the FPGA at run time, as well
as remote patching for upgrading, remote
debugging, and remote repair by reconfiguration -
even over the internet.
30gtgt Run-Time Reconfiguration (RTR)
- Configware Market
- FPGA Market
- Embedded Systems (Co-Design)
- Hardwired IP Cores on Board
- Run-Time Reconfiguration (RTR)
- Rapid Prototyping ASIC Emulation
- Evolvable Hardware (EH)
- Academic Expertise
- ASICs dead
- Soft CPU
- HLLs
- Problems to be solved
31CPU use for configuration management
- on-board microprocessor CPU is available anyhow -
even along with a little RTOS - use this CPU for configuration management
RTR System Design
32hard CPU memory core on same chip
33Converging factors for RTR
- Converging factors make RTR based system design
viable - 1) million gate FPGA devices and co-processing
with standard microprocessors are commonplace - direct implementation of complex algorithms in
FPGAs. - This alone has already
revolutionized FPGA design. - 2) new tools like Xilinx Jbits
software tool suite directly
support
coprocessing and RTR.
34RTR
- divides application into a series of sequentially
executed stages, each implemented as a separate
execution module. - Partial RTR partitions these stages into
finer-grain sub-modules to be swapped in as
needed. - Without RTR, all conf. platforms just ASIC
emulators. - needs a new kind of application development
environments. - directly support development and debugging of RTR
appl. - essential for the advancement of configurable
computing - will also heavily influence the future system
organization - Xilinx, VT, BYU work on run-time kernels,
run-time support, RTR debugging tools and other
associated tools. - smaller, faster circuits, simplified hardware
interfacing, fewer IOBs smaller, cheaper
packages, simplified software interfaces.
35Run-time Mapping
- run-time reconfigurable are Xilinx VIRTEX FPGA
family - RAs being part of Chameleon CS2000 series systems
- Using such devices changes many of the basic
assumptions in the HW/SW co-design process - host/RL interaction is dynamic, needs a tiny OS
like eBIOS, also to organize RL reconfiguration
under host control - typical goal is minimization of reconfiguration
latency (especially important in communication
processors), to hide configuration loading
latency, and, - Scheduling to find best schedule for eBIOS
calls (Cside).
36gtgt Rapid Prototyping ASIC Emulation
- Configware Market
- FPGA Market
- Embedded Systems (Co-Design)
- Hardwired IP Cores on Board
- Run-Time Reconfiguration (RTR)
- Rapid Prototyping ASIC Emulation
- Evolvable Hardware (EH)
- Academic Expertise
- ASICs dead
- Soft CPU
- HLLs
- Problems to be solved
37ASIC emulation a new business model ?
- ASIC emulation / Rapid Prototyping to replace
simulation - Quickturn (Cadence), IKOS (Synopsys), Celaro
(Mentor) - from rack to board to chip (from other vendors,
e. g. Virtex and VirtexE family (emulate up to 3
million gates) - Easy configuration using SmartMedia FLASH cards
- ASIC emulators will become obsolete within years
- By RTR in-circuit execution debugging instead of
emulation
38gtgt Evolvable Hardware (EH)
- Configware Market
- FPGA Market
- Embedded Systems (Co-Design)
- Hardwired IP Cores on Board
- Run-Time Reconfiguration (RTR)
- Rapid Prototyping ASIC Emulation
- Evolvable Hardware (EH)
- Academic Expertise
- ASICs dead
- Soft CPU
- HLLs
- Problems to be solved
39EH, EM, ...
- "Evolvable Hardware" (EH), "Evolutionary Methods"
(EM), digital DANN, "Darwinistic Methods", and
biologically inspired electronic systems - new research area, also a new application area of
FPGAs - revival of cybernetics or bionics stimulated by
technology - evolutionary and DNA metaphor create
awareness - EM sucks, also thru mushrooming funds in the EU,
in Japan, Korea, and the USA - EM-related international conference series are in
their stormy visionary phase, like EH, ICES,
EuroGP, GP, CEC, GECCO, EvoWorkshops, MAPLD, ICGA
40EH, EM, ...
- Shake-out phenomena expected, like in the past
with Artificial Intelligence - should be considered as a specialized EDA scene,
focusing on theoretical issues. - Genetic algorithms suck - often replacable by
more efficient ones from EDA - It is recommendable to set-up an interwoven
competence in both scenes, EM scene and the
highly commercialized EDA scene - EH should be done by EDA people, rather than EM
freaks.
41gtgt Academic Expertise
- Configware Market
- FPGA Market
- Embedded Systems (Co-Design)
- Hardwired IP Cores on Board
- Run-Time Reconfiguration (RTR)
- Rapid Prototyping ASIC Emulation
- Evolvable Hardware (EH)
- Academic Expertise
- ASICs dead
- Soft CPU
- HLLs
- Problems to be solved
42BRASS (1)
- UC Berkeley, the BRASS group Prof. Dr. John
Wawrzynek - The Pleiades Project, Prof. Jan Rabaey, ultra-low
power high-performance multimedia computing
through reconfiguration of heterogeneous system
modules, reducing energy by overhead elimination,
programmability at just right granularity,
parallellism, pipelining, dynamic voltage
scaling. - Garp integrates processor and FPGA dev. in
parallel w. compiler - software compile
techniques (VLIW SW pipelining) simple
pipelining schema f. broad class of loops. - SCORE, a stream-based computation model - a
unifying computational model. Fast Mapping for
Datapaths by a tree-parsing compiler tool for
datapath module mapping
43BRASS (2)
- HSRA. new FPGA ( related tools) supports
pipelining, w. retiming capable CLB architecture,
implemented in a 0.4um DRAM process supporting
250MHz operation - OOCG. Object Oriented Circuit-Generators in Java
- MESCAL (GSRC), the goal is to provide a
programmer's model and software development
environment for efficient implementation of an
interesting set of applications onto a family of
fully-programmable architectures /
microarchitectures.
44Berkeley claiming (1)
- SCORE, a stream-based computation model the
BRASS group claims having solved the problem of
primary impediment to wide-spread reconfigurable
computing, by a unifying computational model. - Remark clean stream-based model introduced
1980 Systolic Array - 1995 Rainer Kress. Introduces reconfigurable
stream-based model - Fast Mapping for Datapaths (SCORE) BRASS claims
having introduced 1998 the first tree-parsing
compiler tool for datapath module mapping ."
Further, it is the first work to integrate
simultaneous placement with module mapping in a
way that preserves linear time complexity."
45Berkeley claiming (2)
- Remark The DPSS (Data Path Synthesis System)
using tree covering simultanous datapath
placement and routing has been published in 1995
by Rainer Kress - Chip-in-a-Da2 Bee Project. Prof. Dr. Bob
Brodersons radical rethink of the ASIC design
flow aimed at shortening design time, relying on
stream-based DPU arrays. published in 2000 - Remark the KressArray, a scalable rDPU array
1995 is stream-based
46.... Stream Processors - MSP-3
- 3rd Workshop on Media and Stream Processors
(MSP-3) - http//www.pdcl.eng.wayne.edu/msp01
- in conj. w. 34th Intl Symp. on Microarchitecture
(MICRO-34) - http//www.microarch.org/micro34
- Austin, Texas, December 1-2, 2001
- Topics of interest include, but are not limited
to - Hardware/Compiler techniques for improving memory
performance of media and stream-based processing - Application-specific hardware architectures for
graphics, video, audio, communications, and other
media and streaming applications - System-on-a-chip architectures for media stream
processors - Hardware/Software Co-Design of media and stream
processors - and others ....
http//www.microarch.org/micro34
47Berkeley Chip-in-a-Day Bee Project
- Chip-in-a-Day Project. Prof. Dr. Bob Broderson,
BWRD targeting a radical rethink of the ASIC
design flow aimed at shortening design time.
Relying on stream-based DPU arrays (not rDPU and
related EDA tools. Davis ... 50x decrease in
power requ. over typical TI C64X design. - New design flow to break up the highly iterative
EDA process, allowing designers to spend more
time defining the device and far less time
implementing it in silicon. ... developers to
start by creating data flow graphs rather than C
code, - It is stream-based computing by DPU array
(hardwired DPA) - For hardwired and reconfigurable DPU array and
rDPU array
48Stanford thru BYU
- Stanford Prof. Flynn went emeritus, Oskar Menzer
moved to Bell Labs. - no activities seen other than YAFA (yet another
FPGA application) - UCLA Prof. Jason Cong, expert on FPGA
architectures and R P algorithms. 9 projects,
mult. sponsors under California MICRO Program - Prof. Majid Sarrafzadeh directs the SPS project
"versatile IPs, a new routing architecture,
architecture-aware CAD, IP-aware SPS compiler - USC Prof. Viktor Prasanna (EE dept.) works 20
on reconfigurable computing MAARC project,
DRIVE project and Efficient Self-Reconfiguration.
- Prof. Dubois RPM Project, FPGA-based
emulation of scalable multiprocessors. - DEFACTO proj. compilation - architecture-independ
ent at all levels - MIT. MATRIX web pages removed 99. RAW project
a conglomerate - VT. Prof. Athanas Jbits API f. internet RTR
logic (2.7 mio DARPA). w. Prof. Brad Hutchings,
BYU on programming approaches for RTR Systems - BYU. Prof. Brad Hutchings works on the JHDL (JAVA
Hardware Description Language) and compilation of
JHDL sources into FPGAs.
49Toronto thru Karlsruhe
- U. Toronto. Prof. J.Rose, expert in FPGA
architectures and R P alg. - The group has dev. Transmogrifier C, a C compiler
creating netlist for Xilinx XC4000 and Altera's
Flex 8000 and Flex 10000 series FPGAs. - Founder of Right Track CAD Corporation acquired
by Altera in 1999 - Los Alamos National Laboratory, Los Alamos, New
Mexico (Jeff Arnold) Project Streams-C
programming FPGAs from C sources. - Katholic University of Leuven, and IMEC Prof.
Rudy Lauwereins, methods for MPEG-4 like
multimedia applications on dynamically
reconfigurable platforms, on reconf.
instruction set processors. - University of Karlsruhe. Prof. Dr.-Ing. Juergen
Becker hardware/software co-design,
reconfigurable architectures rel. synthesis for
future mobile communication systems synthesis
w. - distributed internet-based CAD methods,
partitioning co-compilers
50gtgt ASICs dead ?
- Configware Market
- FPGA Market
- Embedded Systems (Co-Design)
- Hardwired IP Cores on Board
- Run-Time Reconfiguration (RTR)
- Rapid Prototyping ASIC Emulation
- Evolvable Hardware (EH)
- Academic Expertise
- ASICs dead ?
- Soft CPU
- HLLs
- Problems to be solved
51(When) Will FPGAs Kill ASICs? Jonathan Rose
My Position Jonathan Rose
They Just Dont Know It Yet!
52Why? Jonathan Rose
- You have to fabricate an ASIC
- Very hard, getting harder
- An FPGA is pre-fabricated
- A standard part
- immense economic advantages
53Making ASICs is Damn Difficult Jonathan Rose
- Testing
- Yield
- Cross Talk
- Noise
- Leakage
- Clock Tree Design
- Horrible very deep submicron effects we dont
even know about yet
54Did I Mention Inventory? Jonathan Rose
- ASIC users must predict parts
- 2 or 3 months in advance!
- Never guess the Right Amount
- Make Too Many You Pay holding costs
- Make Too Few Competitor gets the Sale
Jonathan Rose
55Jonathan Rose FPGAs Give You
- Instant Fabrication
- Get to Market Fast
- Fix em quick
- Zero NRE Charges
- Low Risk
- Low Cost at good volume
56FPGAs Too Pricey Too Slow ? Jonathan
Rose
- 9 Times Out of 10
- You make can the thing fast by breaking it into
multiple parallel slower pieces
- Custom IC Designer Can Make Logic
- 20x Faster,
- 20x Smaller than Programmable
57Whats Wrong with This Picture?
What About PLD Cores on ASICs ?
Jonathan Rose
- Still Have to Make the Chip
- Need Two Sets of Software to Build It
- The ASIC Flow
- The PLD Flow
- Have No Idea What to Connect the PLD Pins to
- Chances Are, You Are Going to Get It Wrong!
58Whats Right with This Picture!
Jonathan Rose
- Pre-Fabricated
- One CAD Tool Flow!
- Can Connect Anything to Anything
- PLDs are built for general connectivity
59gtgt Soft CPU
- Configware Market
- FPGA Market
- Embedded Systems (Co-Design)
- Hardwired IP Cores on Board
- Run-Time Reconfiguration (RTR)
- Rapid Prototyping ASIC Emulation
- Evolvable Hardware (EH)
- Academic Expertise
- ASICs dead
- Soft CPU
- HLLs
- Problems to be solved
60Free 32 bit processor core
61Processors in PLDs Excalibur
- High-Speed Processors Integrated with PLDs
62Soft CPU new job for compilers
63Some soft CPU core examples
64Nios Architecture (Altera)
65free DSP or Processor Cores
66FPGA CPUs in teaching and academic research
- UCSC 1990!
- Märaldalen University, Eskilstuna, Sweden
- Chalmers University, Göteborg, Sweden
- Cornell University
- Gray Research
- Georgia Tech
- Hiroshima City University, Japan
- Michigan State
- Universidad de Valladolid, Spain
- Virginia Tech
- Washington University, St. Louis
- New Mexico Tech
- UC Riverside
- Tokai University, Japan
67Xilinx 10Mg, 500Mt, .12 mic
68Soft rDPA feasible ?
rDPU Array
à la S. Guccione
69Array I/O examples
data streams, or, from / to embedded memory banks
rDPU Array
data streams, or, from / to embedded memory banks
à la S. Guccione
70HLL 2 Soft Array
à la S. Guccione
71HLL 2 flex rDPA
à la S. Guccione
72gtgt HLLs
- Configware Market
- FPGA Market
- Embedded Systems (Co-Design)
- Hardwired IP Cores on Board
- Run-Time Reconfiguration (RTR)
- Rapid Prototyping ASIC Emulation
- Evolvable Hardware (EH)
- Academic Expertise
- ASICs dead
- Soft CPU
- HLLs
- Problems to be solved
73HLLs for Hardware Design vs. System Design vs.
RTR System Design
à la S. Guccione
74HLLs for Hardware Design vs. System Design vs.
RTR System Design
à la S. Guccione
75CPU and memory on Chip
à la S. Guccione
76Jbit Environment
à la S. Guccione
77HLLs for Hardware Design vs. System Design vs.
RTR System Design
à la S. Guccione
78Embedded System Design
à la S. Guccione
79gtgt Problems to be solved
- Configware Market
- FPGA Market
- Embedded Systems (Co-Design)
- Hardwired IP Cores on Board
- Run-Time Reconfiguration (RTR)
- Rapid Prototyping ASIC Emulation
- Evolvable Hardware (EH)
- Academic Expertise
- ASICs dead
- Soft CPU
- HLLs
- Problems to be solved
80Why Cant Reconfig. Software Survive?
- Resource constraints/sizes are exposed
- to programmer
- in low-level representation (netlist)
- Design revolves around device size
- Algorithmic structure
- Exploited parallelism
81Schedule
time slot
08.30 10.00 Reconfigurable Computing (RC)
10.00 10.30 coffee break
10.30 12.00 Stream-based Computing for RC
12.00 14.00 lunch break
14.00 15.30 Resources for RC
15.30 16.00 coffee break
16.00 17.30 FPGAs recent developments
17.30 end of seminar thank you for attending