Firmware redesign

1
Front-End Electronics for the Dark Energy Survey
Camera (DECam) T. Shaw, D. Huffman, M. Kozlovsky,
J. Olsen, W. Stuermer (FNAL) M. Barceló, L.
Cardiel (IFAE) J. Castilla, J. DeVicente, G.
Martinez (CIEMAT) P. Moore, R. Schmidt (NOAO) T.
Moore, V. Simaitis (UIUC)
The front-end electronics design for the Dark
Energy Survey Camera (DECam) is based on the
MONSOON Image Acquisition System that was
developed by the National Optical Astronomy
Observatory (NOAO). MONSOON systems are
currently being used to test and characterize
CCDs. The Dark Energy Survey group both in the
U.S. and Spain - will produce custom versions of
these systems for use in the production readout
that will better match the requirements of a
large focal plane of 70 CCDs and the tight
space constraints of a prime focus instrument.
The customization of the MONSOON boards and the
electronics path will be presented.
A New Clock Board Customized for DES
A New 12-channel Board Customized for DES

• New Clock Board is being designed by engineers at
  CIEMAT (Madrid) which will drive many more clock
  lines.
• The current NOAO board provides 32 clocks, the
  new board will provide 135, or enough for 9 CCDs.

• Why We Need to Change the Monsoon Acquisition
  Board?
• System density
• Limited space in proximity to the telescope
• Increasing the Video Channel count to 12 to
  better match the system.
• Improved Control of CCD Biasing.
• Better trimming of HV Bias
• Control of Substrate voltage rise time (Ramp).
• Adding Temperature read back for RTD sensors.

DES Clock Board Concept
CCD 12 Channel Acq. Board Block Diagram
CCD Packaging
CCDs are wire bonded to a polymide board
Hardware redesign

• BIAS section removed
• 4 clock generation channels added
• 135 cable drivers included on board
• 2 CPLD removed

12-channel Board Description

• 12 Video Signal Channels AC Coupled 18-bit ADC
  (same channel design as Monsoon!)
• Dynamic range and Sensitivity 4V pk/pk 15.6uV/ADC
• Dual Slope CDS with DC Restoration
• Offset controlled to maximize dynamic range
• Maximum 250 kpixel/sec
• Noise lt3 ADU rms
• 48 High Voltage Biasing Signals (Telemetry)
• 12 bit DAC adjustable between fixed range.
• 12 bit ADC read back on each Bias channel
• Outputs can be Enabled/Disabled via software
  control
• Micro-Sequencer Pattern Memory
• Drives the Analog Front End circuits when
  triggered across the Back Plane.
• On-Board Temperature Sensor (10 bits)
• 6 Channels for RTD temperature sensors on CCD
• 12 bit ADC with Sensor Current Source
• Single FPGA for control JTAG programmable
• Board Identification
• Unique Digital Serial Number
• Firmware Version

Firmware redesign

• BIAS control removed
• Code integration from 2 CPLDFPGA to 1 FPGA
• New microsequencer development

Clock board status

• Status
• Schematics and layout ready
• Firmware ready for testing
• Prototype is under production

Three active Monsoon systems are being used to
caharcterize CCDs in our lab
Camera Vessel Instrumentation
12 Channel Board Top View
Monsoon Block Diagram
12 Channel Board Bottom View
Master Control Board Upgrades

• Engineers from IFAE (Barcelona) are working on
  upgrading the Master Control Board
• conversion of optical link from Systran to S-Link
• examination of multi-crate synchronization
  protocol