Effective Capacitance Computation for Interconnect Delay Optimization

1
Effective Capacitance Computation for
Interconnect Delay Optimization

• Zhaojun Wo
• ECE697V

2
Problem

• Given capacitance load CL, use repeater
  insertion method, select proper repeater number K
  repeater size H, minimize the delay (A?Z) as
  much as possible
• Difference between traditional repeater
  method1
• Consider the output Load requirement, and the
  wire length is short compare with global
  interconnect
• Traditional repeater method is always
  over-sized,it can be 500 more than optimized
  value2

Source Bakoglu,circuits,interconnections and
package for VLSI,1990,pp211-219
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Problem of Bakoglus method
Problem Oversize effect more than
500! Question Can we use more accurate model?
Source Effects of global interconnect
optimizations on performance estimation of deep
submicron design, Yu Cao,Berkeley, technical
report,2000
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Delay model
Use PI model3 R10.48Rtot
C11/6Ctot C25/6Ctot.
Bakoglus proposed
Total delaygate delaywiring delayLoad
delay Gate delay is over-estimated at Bakoglus
method Here refine the gate delay modeleffective
capacitance method3 Idea, resistor shielding
effect relieve the gate driving point(B)s
effective load. Its a two pole system, use one
effective cap Ceff to grasp the 50 delay
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Delay model - closed form

• Compare with Bakoglus method

• Consider the Resistor shield effect and load
  effect CL-? Ceff
• cubic root ??square root

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Compute Ceff Algorithm

• Ron,Con from simulation
• TND,TDL tabulated
• Numerical solution to output voltage response
  calculation
• easy to incorporate to CAD package

• source,efficient gate delay modeling for large
  interconnect loadsAndrew,Kahng,UCLA,1999

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Evaluate Ceff

• Test-case
• Inverter(10X), 1mm wire. simulate compare with
  PI model
• 100nm Berkeley model
• CL 01p

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Algorithm test-case
Table 1 bakaglus
Note Hmin,Kmin refer CL0
Table 2 Effective cap
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Result evaluationcompare with optimal value
(130nm,CL0)

• Try different H,K value to spice
• Use Numerical method to get the minimal site
  (programming in Matlab)
• H-unit is X10
• 130nm TECH
• CL0
• Our method(107,2.14) is close to optimal value
• Bakoglu (403,2.5)

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Result evaluationcompare with optimal value
(130nm,CL1p)

• 130nm,CL1p
• H-unit X10
• Our value(176,3.3)
• Bakoglu value (403,2.5) nchanged
• Optimal valueabout(150,2)
• Our value is more close to optimal value
• Load effect let optimum value shift right (H
  increase)

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Conclusion

• Effective capacitance method includes the effect
  of the load
• Effective capacitance method is better than
  traditional method

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Future work

• Questions
• Instead to improve gate delay(B), can we
  emphasis on output(out)?
• Can we analysis s1, s2 to predict output
  waveform?
• Step response easy to get closed form, is it
  reasonable?
• Ramp input possible?

assume step input
Vout(t)0.5 to derive the delay
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First Attempt

• Hard to get analytical solution
• Apply numerical method to get solution
• 100nm, CL1p
• T-unit (ns)
• Contour plot is different from previous result

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Reference

• 1 Effects of global interconnect optimizations
  on performance estimation of deep submicron
  design, Yu Cao,Berkeley, technical report,2000
• 2 efficient gate delay modeling for large
  interconnect loadsAndrew,Kahng,UCLA,1999
• 3 OBrien and T.L.Savarino,modeling the
  driving-point characteristic of Resistive
  Interconnect for accurate Delay estimation,Proc.
  Of ICCAD,1989,pp512-515
• 4 J.Qian,S.Pullela and L. Pillage,Modeling the
  effective capacitance for the RC interconnect of
  CMOS gates,IEEE ICCAD 13,1994,pp1526-1535