Interconnect Delay, Crosstalk and Shielding Boyan Semerdjiev Department of Electrical and Computer E

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Interconnect Delay, Crosstalk and
ShieldingBoyan SemerdjievDepartment of
Electrical and Computer Engineering
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Agenda

• Historical trends
• Interconnect Delay Metrics
• Buffer Insertion Option
• Capacitive Coupling
• Shielding Methodology
• Shielding Results
• Conclusion and Future Trends

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Fast Transistors, Slow Interconnects

• Recently, a trend of slowing down the IC
  evolution due to interconnects
• Today 1mm piece of interconnect - over 5 times
  delay and power of the same size transistor
• Interconnect becomes an IC bottleneck beyond
  0.25um
• RC delay does not decrease as rapidly as gate
  delay
• Interconnect Resistance decline is limited by
  increase of squares per interconnect length
• Interconnect Capacitance decline is limited by
  crosstalk
• Reduction of crosstalk is the key for
  interconnect speed-up

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Agenda

• Historical trends
• Interconnect Delay Metrics
• Buffer Insertion Option
• Capacitive Coupling
• Shielding Methodology
• Shielding Results
• Conclusion and Future Trends

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Delay Metrics - Elmore Delay

• Elmore Delay is the first moment of the impulse
  response of the circuit
• This model assumes a step input

Example ED3 C1R1C2(R1R2)C3(R1R2R3)C4(R1R
2R3)C5(R1R2R3)
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Delay Metrics - Resistive Shielding

• Elmore Delay model no longer accurate
• Resistance along the line becomes a shield in
  estimating total capacitance
• As a result, the effective capacitance at a node
  is lower than the total capacitance down the line
• More accurate delay models are necessary

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Delay Metrics - ECM
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• The Effective Capacitance metric allows for
  modeling the entire circuit as a simple p-model
• This model accounts for degradation of the input
  signal along the circuit
• The input admittance of the circuit is given by
• Therefore, the following parameters can be
  modeled as

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Calculating Upstream Admittance Coefficients 8
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Delay Metrics - LnD, D2M and DM1 2

• Second moment of the impulse response
• Lognormal delay metric 7
• LnD is extremely accurate at distant loads (2)
• and very appropriate for shielding purposes
• D2M
• D2M is within 2 of LnD
• DM1
• However, DM1 is not always guaranteed to exist

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Agenda

• Historical trends
• Interconnect Delay Metrics
• Buffer Insertion Option
• Capacitive Coupling
• Shielding Methodology
• Shielding Results
• Conclusion and Future Trends

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Buffer Insertion Along Long Interconnects

• Buffer Insertion is common for speeding-up long
  interconnects
• Delay assumes quadratic dependence on
  interconnect length
• Many buffer insertion methodologies have been
  proposed
• Placing a buffer in the middle of a wire reduces
  the wire component of delay by half

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Additional Delay due to Buffer Insertion

• Additional Buffer Delay is given by
• Ido is the saturation current of the inverter,
  Vdo is the saturation voltage, Vout is the output
  voltage, Rn and Cn are the resistance and
  capacitance between the buffers

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Agenda

• Historical trends
• Interconnect Delay Metrics
• Buffer Insertion Option
• Capacitive Coupling
• Shielding Methodology
• Shielding Results
• Conclusion and Future Trends

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Interconnect Capacitive Coupling

• Capacitively coupled lines are modeled by the
  aggressor-victim structure
• CTOTAL CGROUND k CCOUPLING
• Effective worst-case capacitance is
  significantly increased, thereby, increasing
  worst-case interconnect delay
• Variations in switching conditions induce
  crosstalk noise and effective capacitance
  variations, thereby causing delay variation
• Delay variation, caused by crosstalk noise, can
  cause system malfunction

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Clock Tree Delay Variation and System Malfunction
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Two Coupled Lines and Effective Capacitance

• If the aggressor line switches in the same
  direction simultaneously, then k0.
• ? CTOTAL CGROUND
• If the aggressor line is quiescent, then k1.
• ? CTOTAL CGROUND CCOUPLING
• If the aggressor line switches in opposite
  direction simultaneously, then k2.
• ? CTOTAL CGROUND 2 CCOUPLING

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Reducing Capacitive Coupling

• Capacitive coupling can be reduced by increasing
  inter-wire spacing
• Consumes significant area resources
• Ground shield is inserted to eliminate switching
  between adjacent lines
• Effective capacitance of CGROUND CCOUPLING

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Agenda

• Historical trends
• Interconnect Delay Metrics
• Buffer Insertion Option
• Capacitive Coupling
• Shielding Methodology
• Shielding Results
• Conclusion and Future Trends

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Shielding Along the Direct Path to a Load

• Switching in the same direction
• CSHIELDED gt CNON-SHIELDED
• Best-case delay increases as shielding is
  performed closer to the critical load

• Switching in opposite directions
• CSHIELDED lt CNON-SHIELDED
• Worst-case delay decreases as shielding is
  performed closer to the critical load

• Delay variation at the critical load is reduced
  if shielding is applied closer to the critical
  load on the direct path

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Shielding Along a Line Segment on a Branch

• Switch in the same direction
• CSHIELDED gt CNON-SHIELDED
• Best-case delay increases as shielding is
  performed closer to the direct path to load

• Switch in opposite directions
• CSHIELDED lt CNON-SHIELDED
• Worst-case delay decreases as shielding is
  performed closer to the direct path to load

• Delay variation at the critical load is reduced
  if shielding is applied closer to the direct path
  to the critical load

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Shielding Methodology

• The greatest reduction in delay variation is
  achieved if the load unit segment is shielded
  first
• Shielding along the direct path towards the
  source is performed next
• When branches are reached, the shielding
  frontier advances downstream towards the tree
  terminals and towards the source
• Shielding continues until the resources are
  exhausted

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Agenda

• Historical trends
• Interconnect Delay Metrics
• Buffer Insertion Option
• Capacitive Coupling
• Shielding Methodology
• Shielding Results
• Conclusion and Future Trends

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Shielding Results - Direct Path vs Path-and-Branch
Shielding 30 Direct-Path
Shielding 30 Path-and-Branch
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of Tree Shielded - Path vs PB Approach
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of Direct-Path Shielded - Path vs PB Approach
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Agenda

• Historical trends
• Interconnect Delay Metrics
• Buffer Insertion Option
• Capacitive Coupling
• Shielding Methodology
• Shielding Results
• Conclusion and Future Trends

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Conclusion

• Interconnect is the bottleneck of Integrated
  Circuits today
• Elmore Delay is not sufficiently accurate, better
  models exist
• Crosstalk causes increased worst-case delay and
  delay variation
• Buffer insertion can reduce interconnect delay
• Reduction of delay variation is equivalent with
  worst-case delay reduction at a given node,
  utilizing the given shielding technique
• For best results, shield insertion should start
  close to the load and spread towards the source
  and leaves
• Path-and-branch shielding is more efficient than
  direct-path shielding
• Vertically integrated circuits - shorter wires
  and less crosstalk
• In the future, inductive effects will become a
  serious problem, especially with fast transition
  times and smaller interconnect length

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Bibliography

• 1. Optimal Crosstalk Shielding Insertion Along
  On-Chip Interconnect Trees Boyan Semerdjiev and
  Dimitrios Velenis, VLSI Conference, Jan 2007
• 2. RC Delay Metrics for Performance Optimization
  C. Alpert, A. Devgan, C. Kashyap, May 2001
• 3. Uniform Repeater Insertion in RC Trees V.
  Adler, E. Friedman, Oct 2000
• 4. Beyond Moores Law the Interconnect Era J.
  D. Meindl Georgia Institute of Technology
• 5. Analysis of Interconnect Delay for 0.18um
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• 6. Interconnect Design for Deep Submicron ICs
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  and Kei-Yong Khoo, Computer Science Department,
  University of Califomia, Los Angeles
• 7. Delay and Slew Metrics Using the Lognormal
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• 8. An Effective Capacitance Based Delay Metric
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  Devgan, IBM Corp., 11400 Burnet Road, Austin, TX,
  78758
• 9. Modeling the Driving-Point Characteristic of
  Resistive Interconnect for Accurate Delay
  Estimation P. OBrien, T. Savarino, 1989
• 10. Maximizing Shielding Efficiency on Noisy
  On-Chip Interconnects Boyan Semerdjiev, MS
  Thesis, Illinois Institute of Technology, May 2006