CS184a: Computer Architecture (Structures and Organization)

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CS184aComputer Architecture(Structures and
Organization)

• Day11 October 30, 2000
• Interconnect Requirements

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Last Time

• Saw various compute blocks
• Role of automated mapping in exploring design
  space
• To exploit structure in typical designs we need
  programmable interconnect
• All reasonable, scalable structures
• small to moderate sized logic blocks
• connected via programmable interconnect
• been saying delay across programmable
  interconnect is a big factor

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Today

• Interconnect Design Space
• Dominance of Interconnect
• Simple things
• and why they dont work
• Interconnect Implications
• Characterizing Interconnect Requirements

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Dominant Area
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Dominant Time
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Dominant Time
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Dominant Power
XC4003A data from Eric Kusse (UCB MS 1997)
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For Spatial Architectures

• Interconnect dominant
• area
• power
• time
• so need to understand in order to optimize
  architectures

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Interconnect

• Problem
• Thousands of independent (bit) operators
  producing results
• true of FPGAs today
• true for LIW, multi-uP, etc. in future
• Each taking as inputs the results of other (bit)
  processing elements
• Interconnect is late bound
• dont know until after fabrication

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Design Issues

• Flexibility -- route anything
• (w/in reason?)
• Area -- wires, switches
• Delay -- switches in path, stubs, wire length
• Power -- switch, wire capacitance
• Routability -- computational difficulty finding
  routes

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(1) Shared Bus

• Familiar case
• Use single interconnect resource
• Reuse in Time
• Consequence?

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Shared Bus

• Consider operation yAx2 Bx C
• 3 mpys
• 2 adds
• 5 values need to be routed from producer to
  consumer
• Performance lower bound if have design w/
• m multipliers
• u madd units
• a adders
• i simultaneous interconnection busses

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Viewpoint

• Interconnect is a resource
• Bottleneck for design can be in availability of
  any resource
• Lower Bound on Delay
• Logical Resource / Physical Resources
• May be worse
• dependencies
• ability to use resource

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Shared Bus

• Flexibility ()
• routes everything (given enough time)
• can be trick to schedule use optimally
• Delay (Power) (--)
• wire length O(kn)
• parasitic stubs knn
• series switch 1
• O(kn)
• sequentialize I/B

• Area ()
• kn switches
• O(n)

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Term Bisection Bandwidth

• Partition design into two equal size halves
• Minimize wires (nets) with ends in both halves
• Number of wires crossing is bisection bandwidth

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(2) Crossbar

• Avoid bottleneck
• Every output gets its own interconnect channel

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Crossbar
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Crossbar
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Crossbar

• Flexibility ()
• routes everything (guaranteed)
• Delay (Power) (-)
• wire length O(kn)
• parasitic stubs knn
• series switch 1
• O(kn)

• Area (-)
• Bisection bandwidth n
• kn2 switches
• O(n2)

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Crossbar

• Too expensive
• Switch Area kn22.5Kl2
• Switch Area/LUT kn 2.5Kl2
• n1024, k4 gt 10M l2
• What can we do?

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Avoiding Crossbar Costs

• Typical architecture trick
• exploit expected problem structure

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Avoiding Crossbar Costs

• Typical architecture trick
• exploit expected problem structure
• We have freedom in operator placement
• Designs have spatial locality
• gtplace connected components close together
• dont need full interconnect?

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Exploit Locality

• Wires expensive
• Local interconnect cheap
• 1D versions?
• (explore on hmwrk)

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Exploit Locality

• Wires expensive
• Local interconnect cheap
• Use 2D to make more things closer
• Mesh?

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Mesh Analysis

• Can we place everything close?

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Mesh Closeness

• Try placing everything close

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Mesh Analysis

• Flexibility - ?
• Ok w/ large w
• Delay (Power)
• Series switches
• 1--?n
• Wire length
• w--?n
• Stubs
• O(w)--O(w?n)

• Area
• Bisection BW -- w?n
• Switches -- O(nw)
• O(w2n) linear pop
• larger on homework

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Mesh

• Plausible
• but Whats w
• and how does it grow?

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Characterize Locality

• Want to exploit locality
• How much locality do we have?
• Impact on resources required?

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Bisection Bandwidth

• Bisect design
• Bisection bandwidth of design
• gt lower bound on network bisection bandwidth
• Design with more locality
• gt lower bisection bandwidth
• Enough?

N/2
cutsize
N/2
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Characterizing Locality

• Single cut not capture locality within halves
• Cut again
• gt recursive bisection

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Regularizing Growth

• How do bisection bandwidths shrink (grow) at
  different levels of bisection hierarchy?
• Basic assumption Geometric
• 1
• 1/?
• 1/?2

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Geometric Growth

• (F,a)-bifurcator
• F bandwidth at root
• geometric regression a at each level

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Good Model?
Log-log plot gt straight lines represent
geometric growth
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Rents Rule

• Long standing empirical relationship
• IO CNP
• 0?P ?1.0
• compare (F,a)-bifurcator
• a 2P
• Captures notion of locality
• some signals generated and consumed locally
• reconvergent fanout

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Monday class stopped here
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Rents Rule

• Typically consider
• 0.5?P ?0.75
• High-Speed Logic P0.67
• Memory (P0.1-0.2)
• Example (i10)
• max C7, P0.68
• avg C5, P0.72

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What tell us about design?

• Recursive bandwidth requirements in network

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What tell us about design?

• Recursive bandwidth requirements in network
• lower bound on resource requirements
• N.B. necessary but not sufficient condition on
  network design
• I.e. design must also be able to use the wires

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What tell us about design?

• Interconnect lengths
• Intuition
• if pgt0.5, everything cannot be nearest neighbor
• as p grows, so wire distances

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What tell us about design?

• Interconnect lengths
• IO(n2)P cross distance n
• dIO/dn end at exactly distance n
• E(l)Integral 0 to n?N
• of n(dIO/dn)/n2
• assume iid sources
• E(l)O(N(p-0.5))
• pgt0.5

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What Tell us about design?

• IO?NP
• Bisection BW?NP
• side length ?NP
• N if plt0.5
• Area ?N2p
• pgt0.5

N.B. 2D VLSI world has natural Rent of
P0.5 (area vs. perimeter)
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Rents Rule Caveats

• Modern systems on a chip -- likely to contain
  subcomponents of varying Rent complexity
• Less I/O at certain natural boundaries
• System close
• (Rents Rule apply to workstation, PC, PDA?)

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Area/Wire Length

• Bad news
• Area O(N2p)
• faster than N
• Avg. Wire Length O(N(p-0.5))
• grows with N
• Can designers/CAD control p (locality) once
  appreciate its effects?
• I.e. maybe this cost changes design
  style/criteria so we mitigate effects?

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What Rent didnt tell us

• Bisection bandwidth purely geometrical
• No constraint for delay
• I.e. a partition may leave critical path weaving
  between halves

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Critical Path and Bisection
Minimum cut may cross critical path multiple
times. Minimizing long wires in critical path gt
increase cut size.
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Rent Weakness

• Not account for path topology
• ? Can we define a Temporal Rent which takes
  into consideration?
• Promising research topic

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Finishing Up...
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Big IdeasMSB Ideas

• Interconnect Dominant
• power, delay, area
• Can be bottleneck for designs
• Cant afford full crossbar
• Need to exploit locality
• Cant have everything close

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Big IdeasMSB Ideas

• Rents rule characterize locality
• gt Area growth O(N2p)
• pgt0.5 gt interconnect growing faster than
  compute elements
• expect interconnect to dominate other resources