Process-Variation-Resistant Dynamic Power Optimization for VLSI Circuits

1
Process-Variation-Resistant Dynamic Power
Optimization for VLSI Circuits

• Fei Hu
• Department of ECE
• Auburn University, AL 36849
• Ph.D. Dissertation Committee
• Dr. Vishwani D. Agrawal
• Dr. Foster Dai
• Dr. Darrel Hankerson
• Dr. Saad Biaz (Outside Reader)
• November 16, 2005

2
Outline

• Introduction
• Background
• Dynamic power dissipation
• Glitch reduction
• Previous LP model
• Process-variation-resistant LP model
• Process variation
• Delay model
• LP model based on worst-case timing
• LP model based on statistical timing
• Input-specific optimization
• Without process-variation
• With process-variation
• Experimental results
• Conclusion

3
Introduction

• Power component for CMOS circuits
• Pavg Pstatic Pdynamic
• Pdynamic ? 1/2 kCLVdd2fclk
• Power dissipation problem
• For constant die size, total capacitance
  increases by 40 when transistor size is reduced
  by 70
• Clock frequency is scaled up faster than the
  minimum feature size (MFS)
• Leakage power increases dramatically as MFS
  reduces into submicron region
• Architecture trend is towards programmability and
  reusability leads to more hunger for power

4
VLSI Chip Power Density
Source Intel?
5
Outline

• Introduction
• Background
• Dynamic power dissipation
• Glitch reduction
• Previous LP model
• Process-variation-resistant LP model
• Process variation
• Delay model
• LP model based on worst-case timing
• LP model based on statistical timing
• Input-specific optimization
• Without process-variation
• With process-variation
• Experimental results
• Conclusion

6
Background

• Dynamic power dissipation
• Pdyn Pswitching Pshort-circuit
• Switching power dissipation
• Pswitching 1/2 kCLVdd2fclk

7
Background

• Short-circuit power dissipation
• Short-circuit current when both PMOS and NMOS are
  on
• Very much affected by the rising and falling
  times of input signals
• significant when input rise/fall time much longer
  than the output rise/fall time
• Can be kept to a insignificant portion of Pdyn

8
Background

• Glitch reduction
• A important dynamic power reduction technique
• Glitch power consumes 3070 Pdyn for typical
  circuits
• Related techniques
• Balanced delay
• Hazard filtering
• Transistor/Gate sizing
• Linear Programming approach

9
Glitch reduction

• Original circuit
• Balanced path/ path balancing
• Equalize delays of all path incident on a gate
• Balancing requires insertion of delay buffers.
• Hazard/glitch filtering
• Utilize glitch filtering effect of gate
• Not necessary to insert buffer

10
Glitch reduction

• Transistor/gate sizing
• Find transistor sizes in the circuit to realize
  the delay
• No need to insert buffer
• Suffers from nonlinearity of delay model
• large solution space, numeric convergence and
  global optimization not guaranteed
• Linear programming approach
• Adopt both path balancing and hazard filtering
• Find the optimal delay assignments of gates
• Use technology mappings to map the gate delay
  assignments to transistor/gate dimensions.
• Guaranteed optimal solution, a convenient way to
  solve a large scale optimization problem

11
Previous LP approach
Circuit delay constraints T11 maxdelay T12
maxdelay Objective Minimize sum of buffer delays
Timing window (t, T)
Gate constraints T7 ? T5 d7 T7 ? T6 d7 t7
t5 d7 t7 t6 d7 d7 gt T7 t7
T6
t6
T7
t7
d7
T5
t5
12
Outline

• Introduction
• Background
• Dynamic power dissipation
• Glitch reduction
• Previous LP model
• Process-variation-resistant LP model
• Process variation
• Delay model
• LP model based on worst-case timing
• LP model based on statistical timing
• Input-specific optimization
• Without process-variation
• With process-variation
• Experimental results
• Conclusion

13
Process-variation-resistant optimization

• Motivation
• Gate delay assumed fixed in previous models
• Variation of gate delay in real circuits
• Environmental factors temperature, Vdd
• Physical factors process variations
• Effect of delay variation
• Glitch filtering conditions corrupted
• Power dissipation increases from the optimized
  value
• Leakage variation possible, requires separate
  investigation
• Our proposal
• Consider delay variations in dynamic power
  optimization
• Only consider process variations (major source of
  delay variation)

14
Process and delay variations

• Process variations
• Variations due to semiconductor process
• VT, tox, Leff, Wwire, THwire,etc.
• Inter-die variation
• Constant within a die, vary from one die to
  another die of a wafer or wafer lot
• Intra-die variation
• Variation within a die
• Due to equipment limitations or statistical
  effects in the fabrication process, e.g.,
  variation in doping concentration
• Spatial correlations and deterministic variation
  due to CMP and optical proximity effect

15
Process and delay variations

• Delay variation
• First order gate delay model
• Gate delay sensitive to process-variations
• Related previous work
• Static timing analysis
• Worst case timing analysis
• Statistical timing analysis
• Power optimization under process-variations
• Voltage scaling, multi-Vdd/Vth considering
  critical delay variations
• Gate sizing using statistical delay model
• No work on glitch power optimization

16
Delay model and implications

• Random gate delay model
• Truncated normal distribution
• Assume independence
• Variation in terms of s/Dnom,i ratio
• Effect of inter-die variations
• Depends on its effect to switching activities
• Definition of glitch-filtering probability Pglt
  P t2-t1lt d
• Signal arrival time t1, t2
• Gate inertial delay d
• Theorem 1 states the change of Pglt due to
  inter-die variation
• erf(), the error function
• k, a path and gate dependent constant
• r, s/Dnom,i ratio for inter-die variations

17
Delay model and implications

• Effect of inter-die variations
• For a large inter-die variation, r 0.15,
  ?Pglt lt 5.310-3
• Negligible effect on switching activity

18
Delay model and implications

• Process-variation-resistant design
• Can be achieved by path balancing and glitch
  filtering
• Critical delay may increase
• Theorem 2 states that a solution is guaranteed
  only if circuit delay is allowed to increase
• Proved by example, assuming 10 variation

3.9
2.1
19
LP model based on worst-case timing

• Timing model

20
LP model based on worst-case timing

• Constraints
• Gate constraints
• Glitch filtering constraints
• Delay constraints for POs
• Parameter
• r, s/Dnom,i ratio
• Dmax, circuit delay parameter
• ?, optimism factor ? 1,8 1 all glitches
  filtered, 8 no glitch filtered
• Objective
• Minimize buffer inserted sum of buffer delays

21
LP model based on statistical timing

• Worst-case timing tends to be too pessimistic
• Statistical timing model with random variables

22
LP model based on statistical timing

• Minimum-maximum statistics
• needed for tbi, Tbi
• Previous works
• Min, Max for two normal random variable not
  necessarily distributed as normal
• Can be approximated with a normal distribution
• Requiring complex operations, e.g., integration,
  exponentiation, etc.
• Challenges for LP approach
• Require simple approximation w/o nonlinear
  operations
• Our approximation for CMax(A,B), A, B, and C are
  Gaussian RVs

23
LP model based on statistical timing

• Min-Max statistics approximation error
• Negligible when ?A-?Bgt 3(sA sB)
• Largest when ?A?B

24
LP model based on statistical timing

• Variables
• Timing, delay variables with mean ? and std dev s
• Auxiliary variables,
• Constraints
• Gate constraints
• Timing window at the inputs for a two-input gate
  i
• Timing window at outputs

25
LP model based on statistical timing

• Constraints
• Gate constraint
• Linear approximation
• k ? 0.707, 1 choose k0.85, since
• Glitch filtering constraints
• Circuit delay constraint

26
LP model based on statistical timing

• Parameter
• r, s/Dnom,i ratio
• Dmax, circuit delay parameter
• ?, optimism factor
• ?1, no relaxation
• ?lt1, optimistic about the actual glitch width
• ?0, reduce to previous model
• Objective
• Minimize buffer inserted sum of buffer delays

27
Outline

• Introduction
• Background
• Dynamic power dissipation
• Glitch reduction
• Previous LP model
• Process-variation-resistant LP model
• Process variation
• Delay model
• LP model based on worst-case timing
• LP model based on statistical timing
• Input-specific optimization
• Without process-variation
• With process-variation
• Experimental results
• Conclusion

28
Input-specific optimization

• Motivation
• Previous LP models guarantees glitch filtering
  for any input vector sequence
• Ti - ti lt di for all gates
• Redundancy in optimization
• Insertion of more buffers
• Increased the overhead in power/area
• In reality, circuit under embedded environments
• Optimization for input vector sequence that is
  possible to the circuit, e.g., functional vectors
• Same reduction in power dissipation w/ less
  trade-offs in overheads

29
Input-specific optimization

• Glitch generation pattern
• Input vector pair that can potentially generate a
  glitch
• AND gate example
• Glitch generation probability Pgi
• Probability glitch-generation pattern occurs at
  input of gate i
• Steady state signal values match the pattern

30
Input-specific optimization

• Application to Previous model w/o
  process-variation
• Static optimization
• Only static glitches/hazards considered
• Relaxation of constraints
• Relax glitch filtering constraints where glitches
  unlikely happen
• Ti - ti lt di gt (Ti ti)?i lt di
• Selective relaxation
• Generalized relaxation

31
Input-specific optimization

• Application to process-variation-resistant LP
  model based on statistical timing
• Static optimization
• Relaxation of constraints
• Selective relaxation
• Generalized relaxation
• Tuning factor
• Original objective
• Current objective

32
Input-specific optimization

• Why need a tuning factor
• Dominating path affected critical delay
  distribution

Can be 1,41
Dominating path
41
0
1
1
1
0
1
33
Outline

• Introduction
• Background
• Dynamic power dissipation
• Glitch reduction
• Previous LP model
• Process-variation-resistant LP model
• Process variation
• Delay model
• LP model based on worst-case timing
• LP model based on statistical timing
• Input-specific optimization
• Without process-variation
• With process-variation
• Experimental results
• Conclusion

34
Experimental results

• Experimental procedure
• Flow chart
• Power estimation
• Event driven logic simulation
• Fanout weighted sum of switching activities
• Variations of CL and Vdd ignored
• Monte-Carlo simulation with 1,000 samples of
  delays under process-variation
• Results analysis
• Un-Opt., unit-delay circuit
• Opt, previous optimization
• Opt1, Proc-var-rst optimization worst-case timing
• Opt2, Proc-var-rst optimization statistical
  timing

35
Experimental results small variation

• Power dissipation under no process variation

UnOpt Opt (w/o proc var.) Opt (w/o proc var.) Opt (w/o proc var.) Opt1 (worst case proc) Opt1 (worst case proc) Opt1 (worst case proc) Opt2 (statistical proc) Opt2 (statistical proc) Opt2 (statistical proc)
Pwr. Pwr. Buf. maxdelay Pwr. Buf. Dmax Pwr. Buf. Dmax
c432 1.0 0.74 95 17 0.74 96 20 0.74 99 20
1.0 0.74 66 34 0.74 91 40 0.74 91 40
c499 1.0 0.94 80 11 0.94 88 13 0.94 97 13
1.0 0.94 48 22 0.94 88 26 0.94 129 26
c880 1.0 0.54 63 24 0.54 45 28 0.54 76 28
1.0 0.54 29 72 0.54 37 83 0.54 37 83
c1355 1.0 0.93 224 24 0.93 296 28 0.93 305 28
1.0 0.93 160 72 0.93 296 83 0.93 273 83
c1908 1.0 0.53 84 40 0.53 68 46 0.52 136 46
1.0 0.55 54 120 0.53 92 138 0.52 198 138
c2670 1.0 0.74 157 32 0.79 244 37 0.73 313 37
1.0 0.74 26 96 0.75 80 111 0.73 168 111
c3540 1.0 0.60 219 47 0.59 228 55 0.59 306 55
1.0 0.59 103 141 0.61 152 163 0.59 303 163
c5315 1.0 0.56 281 49 0.62 228 57 0.55 401 57
1.0 0.56 113 147 0.58 130 170 0.55 460 170
c6288 1.0 0.13 881 124 0.15 801 143 0.14 1685 143
1.0 0.13 864 372 0.14 922 428 0.13 1213 428
c7552 1.0 0.52 369 43 0.64 180 50 0.52 464 50
1.0 0.52 62 129 0.56 162 149 0.52 879 149
36
Experimental results small variation

• Power distribution under 5 inter-die, 5
  intra-die variation

Un-Opt Un-Opt Opt (w/o proc var.) Opt (w/o proc var.) Opt1 (worst case proc) Opt1 (worst case proc) Opt2 (statistical proc) Opt2 (statistical proc)
Circuit Maxdelay Mean Max. Dev. Mean Max. Dev. Mean Max. Dev. Mean Max. Dev.
Pwr. () Pwr. () Pwr. () Pwr. ()
c432 17 1.08 17.5 0.78 12.8 0.75 7.0 0.75 4.5
34 1.08 17.5 0.76 8.2 0.74 0.1 0.74 0.1
c499 11 1.06 12.9 1.00 12.6 0.95 0.7 0.95 0.7
22 1.06 12.9 0.99 12.6 0.94 0.0 0.94 0.1
c880 24 1.03 7.1 0.62 23.1 0.58 13.9 0.55 7.5
72 1.03 7.1 0.57 12.8 0.55 1.1 0.54 1.0
c1355 24 1.10 18.1 0.99 10.6 0.96 5.5 0.95 4.2
72 1.10 18.1 0.98 8.8 0.93 0.3 0.93 0.1
c1908 40 1.15 21.0 0.64 28.6 0.62 22.8 0.58 21.6
120 1.15 21.0 0.64 21.5 0.54 5.9 0.54 6.5
c2670 32 1.17 21.8 0.80 11.6 0.81 5.5 0.75 4.8
96 1.17 21.8 0.77 6.1 0.78 5.2 0.74 1.8
c3540 47 1.15 18.9 0.66 15.2 0.65 12.9 0.63 9.7
141 1.15 18.9 0.62 7.2 0.63 5.1 0.59 1.3
c5315 49 1.12 14.9 0.62 13.8 0.67 9.9 0.59 9.1
147 1.12 14.9 0.60 10.3 0.61 6.8 0.56 3.7
c6288 124 1.46 49.9 0.27 131.6 0.28 105.9 0.24 93.6
372 1.46 49.9 0.26 128.3 0.23 76.8 0.18 56.0
c7552 43 1.17 19.6 0.57 12.4 0.72 13.3 0.57 11.8
129 1.17 19.6 0.56 9.3 0.58 5.1 0.53 3.5
37
Experimental results small variation

• Power timing analysis
• Example c432

maxdelay17
maxdelay26
38
Experimental results small variation

• Critical delay distribution
• Similar nominal delay
• Reduced variation by Opt2 for c880, c2670, c5315,
  c7552

Nominal delay
Max. Deviation
39
Experimental results large variation

• Power dissipation under no process-variation

Un-opt. Opt (w/o proc var.) Opt (w/o proc var.) Opt (w/o proc var.) Opt1 (worst case proc) Opt1 (worst case proc) Opt1 (worst case proc) Opt2 (statistical proc) Opt2 (statistical proc) Opt2 (statistical proc)
Pwr. Pwr. Buf. maxdelay Pwr. Buf. Dmax Pwr. Buf. Dmax
c432 1.00 0.74 66 34 0.75 87 50 0.74 88 50
1.00 0.74 58 68 0.74 81 99 0.74 106 99
c499 1.00 0.94 48 22 0.97 88 32 0.94 88 32
1.00 0.94 0 33 0.97 0 48 0.94 129 48
c880 1.00 0.54 35 48 0.58 36 70 0.54 57 70
1.00 0.54 30 120 0.59 29 174 0.54 62 174
c1355 1.00 0.93 192 48 0.95 264 70 0.93 305 70
1.00 0.93 128 120 0.96 264 174 0.93 305 174
c1908 1.00 0.53 62 80 0.55 41 116 0.52 135 116
1.00 0.54 34 200 0.56 12 290 0.52 190 290
c2670 1.00 0.74 34 64 0.80 39 93 0.74 249 93
1.00 0.74 9 160 0.78 95 232 0.73 211 232
c3540 1.00 0.59 139 94 0.62 149 137 0.59 281 137
1.00 0.59 78 235 0.65 52 341 0.59 311 341
c5313 1.00 0.56 167 98 0.66 93 143 0.55 399 143
1.00 0.56 53 245 0.60 144 356 0.55 418 356
c6288 1.00 0.13 870 228 0.14 1303 331 0.13 1121 331
1.00 0.13 857 620 0.13 939 899 0.13 1473 899
c7552 1.00 0.52 91 86 0.69 64 125 0.52 481 125
1.00 0.52 44 215 0.60 622 312 0.52 645 312
40
Experimental results large variation

• Power distribution under 15 intra-die and 5
  inter-die variation

Un-opt Un-opt Opt (w/o proc var.) Opt (w/o proc var.) Opt1 (worst case proc) Opt1 (worst case proc) Opt2 (statistical proc) Opt2 (statistical proc)
Circuit Max- Mean Max. Dev. Mean Max. Dev. Mean Max. Dev. Mean Max. Dev.
delay Pwr. () Pwr. () Pwr. () Pwr. ()
c432 34 1.09 19.8 0.78 12.6 0.78 12.1 0.76 11.1
68 1.09 19.8 0.77 10.3 0.75 6.1 0.74 3.7
c499 22 1.07 14.0 1.02 15.3 0.98 1.7 0.95 2.0
33 1.07 14.0 0.99 10.2 0.97 1.4 0.95 1.0
c880 48 1.04 8.0 0.62 26.5 0.63 15.7 0.59 18.2
120 1.04 8.0 0.60 22.7 0.60 5.6 0.55 8.6
c1355 48 1.13 21.8 1.06 19.7 0.98 7.3 0.98 10.2
120 1.13 21.8 1.05 18.8 0.97 1.7 0.94 3.0
c1908 80 1.16 23.1 0.72 49.6 0.66 30.1 0.64 35.8
200 1.16 23.1 0.66 32.3 0.62 18.8 0.58 21.4
c2670 64 1.19 25.4 0.81 13.6 0.90 16.0 0.80 13.6
160 1.19 25.4 0.80 11.2 0.82 8.6 0.76 6.2
c3540 94 1.16 20.7 0.67 19.5 0.69 16.9 0.66 17.8
235 1.16 20.7 0.66 16.1 0.71 11.7 0.62 10.1
c5313 98 1.13 16.5 0.67 24.6 0.74 16.3 0.63 20.8
245 1.13 16.5 0.64 19.0 0.66 13.9 0.60 13.4
c6288 228 1.45 52.2 0.43 274.3 0.36 193.4 0.38 223.8
620 1.45 52.2 0.41 264.0 0.31 161.5 0.26 125.3
c7552 86 1.17 21.9 0.64 25.8 0.78 16.0 0.59 18.7
215 1.17 21.9 0.60 20.2 0.65 11.2 0.56 11.8
41
Experimental results large variation

• Critical delay distribution
• Similar nominal delay
• Reduced delay variation by Opt2

Nominal delay
Max. Deviation ()
42
Experimental results input-specific optimization

• Application to Opt under no process-variation,
  IS-Opt

Un-Opt Opt (w/o proc var.) Opt (w/o proc var.) Opt (w/o proc var.) IS-Opt (input-specific w/o proc) IS-Opt (input-specific w/o proc) IS-Opt (input-specific w/o proc)
maxdelay Pwr. Pwr. Delay Buffers Pwr. Delay Buffers
c432 34 1.0 0.74 34 66 0.74 35 66
68 1.0 0.74 68 58 0.74 69 41
c499 22 1.0 0.94 22 48 0.94 22 33
33 1.0 0.94 33 0 0.95 33 0
c880 48 1.0 0.54 51 35 0.54 49 32
120 1.0 0.54 121 30 0.54 122 24
c1355 48 1.0 0.93 48 192 0.93 48 113
120 1.0 0.93 121 128 0.93 120 25
c1908 80 1.0 0.53 82 62 0.54 86 52
200 1.0 0.54 203 34 0.53 204 3
c2670 64 1.0 0.74 65 34 0.74 66 30
160 1.0 0.74 163 9 0.74 162 1
c3540 94 1.0 0.59 95 139 0.59 101 122
235 1.0 0.59 239 78 0.59 239 73
c5315 98 1.0 0.56 100 167 0.56 104 170
245 1.0 0.56 249 53 0.56 250 52
c6288 228 1.0 0.13 226 870 0.13 228 870
620 1.0 0.13 620 857 0.13 620 853
c7552 86 1.0 0.52 89 91 0.52 88 84
215 1.0 0.52 220 44 0.52 221 38
43
Experimental results input-specific optimization

• Application to Opt2 under process-variation,
  IS-Opt2 under 15 intra-die and 5 inter-die
  variation

Un-opt. Opt2 (statistical proc) Opt2 (statistical proc) Opt2 (statistical proc) Opt2 (statistical proc) IS-Opt2 (input-specific statistical proc) IS-Opt2 (input-specific statistical proc) IS-Opt2 (input-specific statistical proc) IS-Opt2 (input-specific statistical proc)
Cir. DMax Nom. Nom. Mean Max Dev. No. Nom. Mean Max Dev. No.
Pwr. Pwr. Pwr. () Buf. Pwr. Pwr. () Buf.
c432 50 1.0 0.74 0.76 11.1 88 0.74 0.76 9.3 81
99 1.0 0.74 0.74 3.7 106 0.74 0.74 3.3 76
c499 32 1.0 0.94 0.95 2.0 88 0.94 0.95 1.9 88
48 1.0 0.94 0.95 1.0 129 0.94 0.95 1.8 58
c880 70 1.0 0.54 0.59 18.2 57 0.54 0.59 20.4 38
174 1.0 0.54 0.55 8.6 62 0.54 0.56 9.0 38
c1355 70 1.0 0.93 0.98 10.2 305 0.93 1.01 13.1 253
174 1.0 0.93 0.94 3.0 305 0.93 0.95 4.7 160
c1908 116 1.0 0.52 0.64 35.8 135 0.52 0.64 34.7 107
290 1.0 0.52 0.58 21.4 190 0.52 0.57 18.4 104
c2670 93 1.0 0.74 0.80 13.6 249 0.73 0.79 11.3 186
232 1.0 0.73 0.76 6.2 211 0.73 0.75 4.3 79
c3540 137 1.0 0.59 0.66 17.8 281 0.59 0.65 15.6 247
341 1.0 0.59 0.62 10.1 311 0.59 0.61 7.4 188
c5315 143 1.0 0.55 0.63 20.8 399 0.55 0.63 21.0 389
356 1.0 0.55 0.60 13.4 418 0.55 0.60 13.2 413
c6288 331 1.0 0.13 0.38 223.8 1121 0.13 0.38 225.2 1115
899 1.0 0.13 0.26 125.3 1473 0.13 0.26 125.5 1243
c7552 125 1.0 0.52 0.59 18.7 481 0.52 0.58 18.1 389
312 1.0 0.52 0.56 11.8 645 0.52 0.55 10.9 520
44
Experimental results input-specific optimization

• Trade-off by generalized relaxation
• c432 circuit with varying ? value
• Reduction of buffers with degradation of power
  distribution

45
Experimental results input-specific optimization

• Critical delay
• Similar performance for Opt2 and IS-Opt2

Nominal delay
Max. deviation
46
Outline

• Introduction
• Background
• Dynamic power dissipation
• Glitch reduction
• Previous LP model
• Process-variation-resistant LP model
• Process variation
• Delay model
• LP model based on worst-case timing
• LP model based on statistical timing
• Input-specific optimization
• Without process-variation
• With process-variation
• Experimental results
• Conclusion

47
Conclusions

• Proposed a dynamic power optimization technique
  that is resistant to the process variation
• Consider process-variation in terms of the delay
  variations
• inter-die and intra-die variations
• Prove inter-die variation has negligible effect
  on switching activity and power
• Construct two new LP models
• Worst case timing analysis
• Statistical timing analysis
• Input-specific optimization to reduce number of
  buffers
• Circuit optimized for certain input vector
  sequence
• Experimental results
• Complete suppression of power variation for small
  circuit and variations
• Significant reduction of power and delay
  variations for larger circuit and variations
• 53 reduction in power deviation, 40 reduction
  in delay deviation under 15 intra-die and 5
  inter-die variation
• Input-specific optimization reduces trade-off
  (buffers) significantly w/ equivalent power and
  delay performance
• IS-Opt2 vs. Opt2, Up to 63 reduction of buffer

48
Questions

• For more questions, contact me at
  hufei01_at_auburn.edu