B.Satyanarayana

1
Status report on electronics, trigger and data
acquisition system for the proposed INO prototype
detector

• B.Satyanarayana Department of High Energy
  PhysicsTata Institute of Fundamental
  ResearchHomi Bhabha Road, Colaba, Mumbai, 400
  005E-mail bsn_at_tifr.res.in

2
INO prototype detector

• Detector and signal specifications
• Detector dimensions 1m X 1m X 1m
• 14 layers of RPCs with 6cm iron plates
  interleaved.
• Two signal planes orthogonal to each other and
  each having 32 pick-up strips
• Total channels 32 X 14 X 2 896
• Pulse height 100 to 300mV Rise time lt 1 ns
• Pulse width 50ns Rate 1KHz
•  
• Trigger information
• Expected trigger rate is few Hz
• Required Trigger logic is m X n fold, where
• m 1 to 4 no. of consecutive channels in a
  layer
• n 5 to 1 no. of consecutive layers with m
  fold in each layer
• ie m x n (1 x 5) OR (2 x 4) OR (3 x 3) OR
  (4 x 2)
• Information to be recorded on a trigger
• Absolute arrival time of the trigger
• Track identification (XYZ points in RPC layers)
• Direction of track ( TDC information)

3
Readout scheme for prototype
4
Fast preamplifier

• Provided by Electronic Division, BARC
• Currently being used with avalanche mode
  operation
• Fixed gain (10), single channel, single polarity,
  with discrete components (availability issues)

5
Preamp hybrid

• Bipolar operation tested
• To be packaged into a hybrid (BEL)
• Possible to mount on the RPC pickup strips
• Will improve signal to noise
• Fabrication procedure
• Circuit schematic by BARC
• Layout preparation by BEL (2-3 weeks)
• Pilot production by BEL and validation (1 month)
• Final production (4-6 weeks)

6
16-channel analog front-end

• Based on Analog Devices Quad-device
• Fast comparator with ECL outputs
• Wire ORed pre-trigger outputs
• Production board tested with RPC strip signals
• Works as good as commercial units
• Components being procured
• Ready for production (2-3 months)

7
32-channel digital front-end
8
Digital front-end status

• Logic fused into a CPLD XC 95288 -HQ708
• Code tested on a simulator and hardware using a
  pattern generator
• Jig fabricated to test the logic on RPC signals
• Work in progress (2 weeks)
• PCB layout is also in progress
• Production estimate about 3 months

9
Prototype detector trigger logic
10
CAMAC based trigger module
m-Fold LVDS signals (X-Plane)
m-Fold LVDS signals (Y-Plane)
Final trigger
11
Trigger module status

• Being developed by Electronics Division, BARC
• Implemented using a FPGA
• Major part of logic coded scalers to be done
• Module given for fabrication
• Expected to be ready in two months
• Testing and debugging (1 month)

12
CAMAC based control module
Generates three sets of control and hand shake
signals for selection of DFE board, readout of
event data and monitoring of pickup signals in
the selected board
13
CAMAC based readout module

• Four serial event data read out channels
• Eight monitor data inputs
• Serial to parallel conversion of event data
• Data written into FIFO buffer
• FIFO buffers readout through CAMAC backplane in
  the event routine
• Eight selected monitor channels translated into
  ECL logic signals
• Rates monitored through ECL input CAMAC scaler
  modules

14
Other items

• High voltage supplies (CAEN, SINP)
• Low voltage supplies (Local)
• Components, cables etc
• Commercial/available modules
• TDCs
• Scalers
• CAMAC crates and controllers
• DAQ software on Linux platform

15
Thoughts for final detector

• Expertise from TIFR, BARC, SINP, VECC, IITB,
  IGCAR, NSC etc
• Industry ready and active
• Front-end and timing ASICs
• Low rates high degree of multiplexing possible
• ASIC design process must begin now
• Comparator ASIC work by SINP
• Tools and training of personnel
• Discussion meeting at national level