Computer Aided Design CAD tools

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Computer Aided Design CAD tools
System Description Languages (System C)
Hardware Description Languages, Schematic
Editors (verilog, VHDL)
Logic Synthesis Tools (Synopsys)
Physical Synthesis Tools (Place Root)
Tape out and Manufacture
2
HW Courses
HY225 ??????s? ?p?????st?? HY425 ????te?t?????
?p?????st?? HY534 ????t. ?eta??????
?a??t?? HY220 ???ast???? ??f. ?????µ. HY120
??f?a?? S?ed?as? HY590.24 ???????µ?? CAD
e??a?e??? HY422 ??sa???? st? VLSI
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Design Verification
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Verification - Simulation
Consistency same testbench at each level of
abstraction
Slower Simulation - Closer to reality
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Automated Verification - Golden Model
Test Vectors Generator (C, perl)
Test Vectors
Golden Model (C, perl)
Testbench (verilog)
Design under test (verilog)
Result Vectors
Same?
Result Vectors
No then test failed, check why
Yes then test passed, run new
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Verification Mixed Mode
Testbench (verilog)
Design under test
RTL blocks (verilog)
Accurate simulation/verification just for some
specific blocks. No need for the whole design.
gate-level blocks (verilog)
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Electronic Design Automation (EDA) tools
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EDA tools (contd)