Electronics

1
Electronics

• Status of the MEG Trigger system
• Status and plans for DAQ
• MSCB slow control system

2
The Trigger System of the MEG Experiment
On behalf of M. Grassi D. Nicolò F. Morsani
S. Galeotti S. Giurgola
3
Expected Trigger Rate

• Accidental background and
• Rejection obtained by applying cuts on the
  following variables
• photon energy
• photon direction
• hit on the positron counter
• time correlation
• positron-photon direction match

The rate depends on R? Re ? R?2
4
The trigger implementation

• Digital approach
• Flash analog-to-digital converters (FADC)
• Field programmable gate array (FPGA)

• Final system
• Only 2 different board types
• Arranged in a tree structure on 3 layers
• Connected with fast LVDS buses
• Remote configuration/debugging capability

• Prototype board
• Check of
• the FADC-FPGA compatibility
• chosen algorithms
• synchronous operation
• data transmission

5
The board type 0
control signals.
LVDS transm.
Differential drivers
PMT inputs
FPGA
FADC
LVDS receiv.
configuration EPROMS
package error solved with a patch board
6
Prototype system configuration
Board 1
input
output
16 PMT
Board 0
Diff. driver
Proc. Algor.
Fadc
16 PMT
input
Last BVR conclusions The prototype system met all
requirements It is available to trigger the LP in
future beam tests
output
LVDS Tx
Proc. Algor.
LVDS Rx
Circ. buff
Circ. buff
LVDS in
final
7
Trigger system structure
2 VME 6U 1 VME 9U Located on the platform
2 boards
LXe inner face (312 PMT)
LXe lateral faces (208 PMT) (120x2 PMT) (40x2 PMT)
1 board
1 board
2 x 48
2 or 1 boards
Timing counters (160 PMT) or (80 PMT)
8
Type 1
LVDS Rx
Proc. Algor.
LVDS Rx
10 type1
LVDS Rx
Type 2
LVDS Tx
Opt. Proces. Algor.
LVDS Tx
Circ. buff
9

• Software items
• New package ISE 6.2
• Verilog/schematic implementation
• Block transfer in A32D16 format (VME library to
  be modified)
• Hardware items
• JTAG programming/debugging through VME by
  modifying the Type0
• Analog receivers and with DACs for pedestal
• FPGA selected VirtexII PRO
• On Type 1 XC2VP20-5-FF1152
• On Type 2 XC2VP40-5-FF1152
• Other components are fixed
• FADC
• LVDS Tx and Rx
• Clock distributor
• Analog input by 3M coaxial connectors
• LVDS connection by 3M cables
• Ancillary logic components and scheme

10
FPGA

• VIRTEX II - PRO
• easily at 100MHz
• 60 of IO
• 40 of CLB
• 2 PowerPC (not used)

11
Analog receiver
Differential driver DAC pedestal control
AD5300
AD8138
12

• Analog receiver
• 16 channels on a type1 board
• 1 unit wide

13
DC/DC converter

• 1.5 Volts
• 3.3 Volts

14
ANCILLARY TREE
START
ANCILLARY 0
TRIGGER
VME
STOP
STOP
SYNC
CLK INT
START, STOP, SYNC, CLK
ANCILLARY 1
ANCILLARY 8

( 16)
CLK EXT
CLK EXT

15
ANCILLARY BLOCKS
TTL2LVDS
INPUTS CLK GEN CLK - START - STOP - SYNC
VME INTERFACE
4 x 8(16)-LVDS-FANOUT
4 x SILICON DELAYS START, STOP, SYNC, CLK
16
ANCILLARY INPUTS CLOCK GEN
INPUT CONNECTOR
LVDS-to-TTL
10MHz CLK GEN
INT/EXT SELECT
17
ANCILLARY SILICON DELAY
18
ANCILLARY LVDS FANOUT
19
Trigger
2002
2003
2004
2005
Prototype Board
Final Prototype
Full System
Prototype Board
Final Prototype
Full System
part. inst.
full. inst.
Test
Milestone
Assembly
Design
Manufactoring
20
summary

• Components selected
• Algorithms implemented
• PCB design ready to start

21
Status and plans for DAQ
22
Domino Chip Principles
Phase and Frequency Stabilization
Trigger Signal Sampling
domino wave
FADC
8 inputs
DLL
Vspeed
External Common Reference Clock
shift register
Low-jitter clock
MUX
16-bit DAC
uC
Freq. Cntr
23
Timing reference
signal
20 MHz clock
PMT hit
Domino stops after trigger latency
24
Recovery of Timing
4) Timing of all PMT pulses is expressed relative
to t0 point
1) Trigger publishes phase f of trigger signal f
relative to clock in multiples of 10 ns
f
50 ns
2) Each DAQ card determines and fits
Time-Zero-Edge in clock signal and uses this as
t0
3) Measure pulse width of clock to derive domino
speed
Domino speed stability of 10-3 400ps
uncertainty for full window 25ps uncertainty
for timing relative to edge
25
Current readout mode

• First implemented in DRS2
• Sampled charge does not leave chip
• Current readout less sensitive to cross-talk etc.

R
I
Vin
Vout
read
write
. . .
C
26
DRS2 Chip

• DRS2 design
• Up to 4.5 GHz sampling speed
• 82 channels, 1024 bins deep each
• Readout speed up to 100 MHz (?)
• Submitted to UMC in Nov. 18th, 58 chips received
  in Jan. 15th, packaging 3 weeks
• DRS2 chip arrived in Feb. 04
• 50 packaged chips (400 channels)
• 1.5 GHz 4.5 GHz sampling speed
• Current mode readout works
• Jitter estimation 40ps
• Plans
• VME prototype board by Aug. 04

27
DRS2 chip
28
DRS2 tests
29
Sampling Speed Measurement

• Obtained last week with USB-Mezzanine board
• Usable sampling range 0.6 GHz 4 GHz

30
Jitter estimation

• Oscilloscope triggered with Domino pulse
• Show 250 turns later
• 11ns/250 44ps
• Should be improved with better board design

31
Analog readout

• 4 pulses, 12ns wide, 1ns rise time digitized at
  2.5 GHz
• Readout at 40 MHz
• Reproduced rise time 1.2ns
• Tests with FADC will follow

32
VME boards with Mezzanine Cards
R. Paoletti INFN Pisa MAGIC collaboration
PSI GVME board
33
PSI GVME Board
34
VME Transition Boards

• PMT/DC signals through front-panel connectors to
  CMC cards with DRS
• Low-jitter clock through front-panel ch. 17
• Trigger, reset, etc through transition board
• Read feedback to trigger thorough transition
  board

Clock
PMTs
Clock
35
DAQ System
area
800 160
3m
Trigger
Active Splitter
11m
31 VME crates
PMT
monitor
trigger
ready
5 VME crates
3m
optical fiber (20m)
DRS Board (32chn) CPU
Front-End PCs
Rack PC (Linux)
SIS 3100
Rack PC (Linux)
Rack PC (Linux)
1920
7m
Rack PC (Linux)
DRS Board (32chn) CPU
DC
Pre-Amp
Rack PC (Linux)
Gigabit Ethernet
backpressure
Rack PC (Linux)
Rack PC (Linux)
Rack PC (Linux)
Raw data 2880 channels 100 Hz 50 / 10 / 10
occupancy 2kB / waveform -gt 5 x 25 MB/sec.
Rack PC (Linux)
Rack PC (Linux)
Fitted data 10 Hz waveform data -gt 1.2
MB/sec 90 Hz ADC / TDC data -gt 0.9 MB/sec
Rack PC (Linux)
On-line farm
storage
36
Rack Layout
Clock distribution (front)
Trigger Board ready Fast clear Event
counter (transition cards)
?
Splitter Trigger DRS Interface
DC
CaloTC
37
HV
HV
DAQ CaloTC
Splitter
Trigger
DAQ DC
38
Electronics in B-Field

• B. Allongue (PH-ESS Group, Cern)
• Wiener PL500 Power Supply works up to 300 Gauss
  (900 with water cooling)
• Fan works up to 80-100 Gauss
• Ordered normal crate for tests
• Need air ducts with external A/C if problems arise

Gauss
Fringing field measured at pE5
4.2
6.8
9.1
6.7
18.5
83.8
50.5
9.0
33.5
433.7
440.3
31.2
7.5
73.3
20.4
56.3
69.7
19.8
7.8
11.6
11.3
39
Waveform analysis
Original Waveform

• Zero suppression in FPGA
• Single hit
• ADC/TDC derived in FPGA
• Multiple hit
• Waveform compressed in FPGA (2x12 bit -gt 3 Byte)
• Waveform fitted / compressed in PC cluster
• Store ADC/TDC only for calibration events
• Store (lossless) compressed waveforms for MEG
  candidates

Region for pedestal evaluation
T
integration area
Difference Of Samples
Threshold in DOS
ADC2/TDC2
ADC1/TDC1
40
Differential DRS channels
cross-talk
Vin

• Measured for
• 1ns rise-time
• 6 neighbor
• 2 next nb

write
Vin
write
Differential Driver
signals cancel
Vin -
41
DRS3

• DRS2 can probably initially be used for DAQ (have
  400 channels, can produce 400 more)
• DRS2 limitations
• Only two channels are fully differential (others
  show larger crosstalk)
• Some tests remain to be done
• New DRS3 design
• All channels differential
• Additional shielding between channels (ground
  bond wires)
• Reduced readout time (5x) minimized dead time
• Internal cascading allows for n x 1024 sampling
  bins

42
Plans

• DRS2 VME prototype board Aug. 04
• Measure all parameters (cross-talk, resolution,
  stability)
• Produce VME boards and equip with DRS2 chip (400
  chn 400 chn ?), install as much as possible in
  are in summer 2005
• Design DRS3 in parallel
• Mass production of DRS3 in fall 2005
• Replace installed DRS2 with DRS3

43
DRS (DAQ)
2002
2003
2004
2005
Tests
DRS1
2nd Prototype
DRS2
Boards Chip
Test
DRS1
DRS2
Optional DRS2 production 400 chn
DRS2 test board
DRS3
Mass Production
400 chn
400 chn
3000 chn
VME boards
Full System
installation
Milestone
Test
Assembly
Design
Manufactoring
44
Slow Control System

• Unified control system for
• Cryogenics (temperature, pressure, valves, etc.)
• Environment (temperatures, crates)
• Drift chamber gas system (pressure, mass flow,
  temperature)
• High Voltage (CaloTCDC, 1000 chn.)
• System must be fail-safe

45
Slow Control
HV
Temperature, pressure,
Valves
12345
Terminal Server
PLC
RS232
GPIB
???
15 C
Ethernet
heater
MIDAS DAQ
46
Slow Control Bus
HV
Temperature, pressure,
Valves
heater
MIDAS DAQ
47
Field Bus Solutions

• CAN, Profibus, LON available
• Node with ADC gt100
• Interoperatibility not guaranteed
• Protocol overhead
• Local CPU? User programmable?
• How to integrate in HV? (CAEN use CAENET)

48
Hardware Overview

• 8051-compatible mC with
• ADC 12-bit
• DAC 12-bit
• Flash EEPROM
• Timers
• Watchdog
• Temperature sensor
• UARTs
• Up to 100MHz clock speed
• External signal conditioning if needed
• Serial communication

49
RS-485 bus

• Similar to RS-232 but
• Up to 256 (1/8 load) units can be connected to a
  single segment, use repeater for more
• Address space for 65536 nodes
• single line, half duplex
• differential twisted pair
• Segment length up to km (20 m tested)
• MSCB system 115kbit
• Single Master Multiple Slaves (like USB)
• Power through bus (10-wire flat ribbon)
• PC USB interface

50
Generic node SCS-200

• C8051Fxxx Micro controllers with 8x12 bit ADC,
  2x12 bit DAC, digital IO, 8051 mC and 32kB Flash
  Memory
• RS-485 bus over flat ribbon cable
• Powered through bus
• Costs CHF 50
• Piggy back board for signal conditioning cards
• 32 kB for real time C programs

51
2 Versions
BUS Oriented

• Generic node with signal conditioning
• RS232 node with protocol translator
• PC connection to parallel port (USB planned)
• Integration on sensors, in crates

52
SCS Nodes

• SCS 210 RS232 I/O
• SCS 300 Centronics I/O (14 bit digital)
• SCS 310 GPIB (IEEE-488) I/O
• SCS 400 8 chn. Thermocouple 4 chn. digital
  output (PWM), temp. regulation in SW
• SCS 500 8 chn. differential analog input 010V,
  01V, 0100mV, 010mV -1010V, -11V,
  -100mV100mV 0100mA, 010mA, 01mA 15V power,
  Lemo or screw terminal
• SCS 600 8 chn. digital output 030V, 1A LEDs
  and buttons on front panel 220V power box
• SCS 700 8 chn. PT100/PT1000, 8 bit digital
  output
• SCS 800 8 chn. capacitance meter
• SCS 900 8 chn. 24-bit ADC -10V10V 8 chn.
  16-bit DAC -10V10V

53
Software overview
SCS xxx
msc.exe Command line interface
LabView Application
Framework
VI
VI
VI
VI
User code
mscb.dll
PC
LPT
USB
SCS 250
SCS 300
RS485
54
Remote access
msc.exe Command line interface
msc.exe Command line interface
LabView Application
VI
VI
VI
VI
TCP/IP
mscb.dll
mscb.dll
PC
PC
LPT
USB
SCS 250
Speed (commands/sec, 115kBaud) 1500 local 900
remote
RS485
55
Protocol

• Asynchronous 345 kBaud / 115kBaud
• 16-bit addressing (65536 nodes)
• CRC-code for error detection
• Optional acknowledge
• Concept of channels and configuration parameters
  (256 each per node)
• Optimized protocol 1500 cmd/sec _at_ 345kB

node
channel1
param1
ADC
channel2
param2
ADC
param3
channel3
port
acknowledge
command
CRC
56
Node communication
msc.exe
LabView
57
Labview control of Large Prototype
58
How to make it fail-safe?

• Robust protocol
• CRC code
• Automatic reconnect
• UPS
• SC crates on battery (30 min.)
• Use Laptop for control PC
• Redundancy
• Operate two completely independent nets
• Switch between nets on failure

59
Redundancy
Switch box
Temperature, pressure,
Valves
Ethernet
Control PC1
System 1
uC
uC
uC
Control PC2
System 2
uC
uC
uC

• If uC fails, use other system
• If PC fails, use other system (PC-PC watchdog)
• For critical valves, use two (parallel or serial)
• Avoid single point of failure !
• Test failures

60
New HV Design
Vin

• Microcontroller optically decoupled from HV side
• Higher ADCDAC resolutions
• 10 mV accuracy
• Stable operation in lab (weeks)
• Newer test results will be presented in review

3000V
12 times
Micro Controller
ADC 24 - bit
Vout
0-3000V
DAC 16 - bit
61
Integration of Slow Control into DAQ

• Run parameters will be written to MySQL database
• Calibration parameters recalculated after every
  run and stored in DB
• More frequent database update possible
• Use of MIDAS history system (widely established
  since many years)

• Display through Web interface
• Gif images generated dynamically in memory
• Command line query with mhist
• Write speed 2000 events/s
• Query over one month in 10sec

Combines Slow Control, monitoring and calibration
data
62
Summary Midas Slow Control Bus

• 256 nodes, 65536 nodes with one level of
  repeaters
• Bus length 500m opto-isolated
• Boards for voltage, current, temperature, Digital
  IO, 220V
• Readout speed 700 channels / sec. _at_ 115kBaud
• C library, command-line utility, Midas driver,
  LabView driver
• Nodes are self-documenting
• Configuration parameters in EEPROM on node
• Node CPU can operate autonomously for interlock
  and regulation (PID) tasks (C programmable,
  floating point library)
• Nodes can be reprogrammed over network
• http//midas.psi.ch/mscb

63
Conclusions

• Trigger system is on schedule
• DRS2 chip works
• Partial electronics installation until mid-2005
  planned
• Slow control system works (as tested in 10
  installations at PSI and TRIUMF)