VHDL Coding Exercise 4: FIR Filter

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VHDL CodingExercise 4 FIR Filter
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Where to start?
Designspace Exploration
Feedback
Algorithm
Architecture
Optimization
RTL- Block diagram
VHDL-Code
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Algorithm

• High-Level System Diagram
• Context of the design
• Inputs and Outputs
• Throughput/rates
• Algorithmic requirements
• Algorithm Description
• Mathematical Description
• Performance Criteria
• Accuracy
• Optimization constraints
• Implementation constraints
• Area
• Speed

FIR
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Architecture (1)

• Isomorphic Architecture
• Straight forward implementation of the algorithm

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Architecture (2)

• Pipelining/Retiming
• Improve timing

• Insert register(s) at the inputs or outputs
• Increases Latency

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Architecture (2)

• Pipelining/Retiming
• Improve timing

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Architecture (2)

• Pipelining/Retiming
• Improve timing

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Architecture (2)

• Pipelining/Retiming
• Improve timing

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Architecture (3)

• Retiming and simple transformation
• Optimization

• Reverse the adder chain

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Architecture (3)

• Retiming and simple transformation
• Optimization

• Reverse the adder chain

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Architecture (3)

• Retiming and simple transformation
• Optimization

• Reverse the adder chain
• Perform Retiming

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Architecture (3)

• Retiming and simple transformation
• Optimization

• Reverse the adder chain
• Perform Retiming

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Architecture (3)

• Retiming and simple transformation
• Optimization

• Reverse the adder chain
• Perform Retiming

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Architecture (3)

• Retiming and simple transformation
• Optimization

• Reverse the adder chain
• Perform Retiming

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Architecture (3)

• Retiming and simple transformation
• Optimization

• Reverse the adder chain
• Perform Retiming

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Architecture (3)

• Retiming and simple transformation
• Optimization

• Reverse the adder chain
• Perform Retiming

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Architecture (3)

• Retiming and simple transformation
• Optimization

• Reverse the adder chain
• Perform Retiming

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Architecture (3)

• Retiming and simple transformation
• Optimization

• Reverse the adder chain
• Perform Retiming

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Architecture (3)

• Retiming and simple transformation
• Optimization

• Reverse the adder chain
• Perform Retiming

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Architecture (3)

• Retiming and simple transformation
• Optimization

• Reverse the adder chain
• Perform Retiming

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Architecture (3)

• Retiming and simple transformation
• Optimization

• Reverse the adder chain
• Perform Retiming

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Architecture (4)

• More pipelining
• Add one pipelining stage to the retimed circuit

• The longest path is given by the multiplier
• Unbalanced The delay from input to the first
  pipeline stage is much longer than the delay
  from the first to the second stage

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Architecture (5)

• More pipelining
• Add one pipelining stage to the retimed circuit

• Move the pipeline registers into the multiplier
• Paths between pipeline stages are balanced
• Improved timing
• Tclock (Tadd Tmult)/2 Treg

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Architecture (6)

• Iterative Decomposition
• Reuse Hardware

• Identify regularity and reusable hardware
  components
• Add control
• multiplexers
• storage elements
• Control
• Increases Cycles/Sample

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RTL-Design

• Choose an architecture under the following
  constraints
• It meets ALL timing specifications/constraints
• Throughput
• Latency
• It consumes the smallest possible area
• It requires the least possible amount of power
• Decide which additional functions are needed and
  how they can be implemented efficiently
• Storage of samples x(k) gt MEMORY
• Storage of coefficients bi gt LUT
• Address generators for MEMORY and LUTgt COUNTERS
• Control gt FSM

Iterative Decomposition
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RTL-Design

• RTL Block-diagram
• Datapath

• FSM
• Interface protocols datapath control

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RTL-Design

• How it works
• IDLE
• Wait for new sample

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RTL-Design

• How it works
• IDLE
• Wait for new sample
• Store to input register

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RTL-Design

• How it works
• IDLE
• Wait for new sample
• Store to input register
• NEW DATA
• Store new sample to memory

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RTL-Design

• How it works
• IDLE
• Wait for new sample
• Store to input register
• NEW DATA
• Store new sample to memory
• RUN

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RTL-Design

• How it works
• IDLE
• Wait for new sample
• Store to input register
• NEW DATA
• Store new sample to memory
• RUN
• Store result to output register

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RTL-Design

• How it works
• IDLE
• Wait for new sample
• Store to input register
• NEW DATA
• Store new sample to memory
• RUN
• Store result to output register
• DATA OUT
• Output result

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RTL-Design

• How it works
• IDLE
• Wait for new sample
• Store to input register
• NEW DATA
• Store new sample to memory
• RUN
• Store result to output register
• DATA OUT
• Output result / Wait for ACK

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RTL-Design

• How it works
• IDLE
• Wait for new sample
• Store to input register
• NEW DATA
• Store new sample to memory
• RUN
• Store result to output register
• DATA OUT
• Output result / Wait for ACK
• IDLE

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Translation into VHDL

• Some basic VHDL building blocks
• Signal Assignments
• Outside a process
• Within a process (sequential execution)

AxD
YxD

• This is NOT allowed !!!

AxD
YxD
BxD

• Sequential execution
• The last assignment is kept when the process
  terminates

AxD
YxD
BxD
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Translation into VHDL

• Some basic VHDL building blocks
• Multiplexer
• Conditional Statements

AxD
BxD
YxD
CxD
SELxS
AxD
BxD
SelAxS
OUTxD
CxD
DxD
SelBxS
STATExDP
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Translation into VHDL

• Common mistakes with conditional statements
• Example

AxD
??

• NO default assignment

SelAxS
OUTxD
BxD

• NO else statement

??
SelBxS
STATExDP

• ASSIGNING NOTHING TO A SIGNAL IS NOT A WAY TO
  KEEP ITS VALUE !!!!! gt Use FlipFlops !!!

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Translation into VHDL

• Some basic VHDL building blocks
• Register
• Register with ENABLE

DataREGxDN
DataREGxDP
DataREGxDN
DataREGxDP
DataREGxDP
DataREGxDN
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Translation into VHDL

• Common mistakes with sequential processes

DataREGxDN
DataREGxDP
CLKxCI

• Can not be translated into hardware and is
  NOT allowed

DataRegENxS
DataREGxDN
DataREGxDP
0
1

• Clocks are NEVER generated within any
  logic

DataREGxDN
DataREGxDP

• Gated clocks are more complicated then this
• Avoid them !!!

CLKxCI
DataRegENxS
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Translation into VHDL

• Some basic rules
• Sequential processes (FlipFlops)
• Only CLOCK and RESET in the sensitivity list
• Logic signals are NEVER used as clock signals
• Combinatorial processes
• Multiple assignments to the same signal are ONLY
  possible within the same process gt ONLY the last
  assignment is valid
• Something must be assigned to each signal in any
  case OR There MUST be an ELSE for every IF
  statement
• More rules that help to avoid problems and
  surprises
• Use separate signals for the PRESENT state and
  the NEXT state of every FlipFlop in your design.
• Use variables ONLY to store intermediate results
  or even avoid them whenever possible in an RTL
  design.

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Translation into VHDL

• Write the ENTITY definition of your design to
  specify
• Inputs, Outputs and Generics

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Translation into VHDL

• Describe the functional units in your block
  diagram one after another in the architecture
  section

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Translation into VHDL

• Describe the functional units in your block
  diagram one after another in the architecture
  section

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Translation into VHDL

• Describe the functional units in your block
  diagram one after another in the architecture
  section

Register with ENABLE
Register with ENABLE
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Translation into VHDL

• Describe the functional units in your block
  diagram one after another in the architecture
  section

Register with CLEAR
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Translation into VHDL

• Describe the functional units in your block
  diagram one after another in the architecture
  section

Counter
Counter
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Translation into VHDL

• Describe the functional units in your block
  diagram one after another in the architecture
  section

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Translation into VHDL

• The FSM is described with one sequential process
  and one combinatorial process

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Translation into VHDL

• The FSM is described with one sequential process
  and one combinatorial process

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Translation into VHDL

• The FSM is described with one sequential process
  and one combinatorial process

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Translation into VHDL

• The FSM is described with one sequential process
  and one combinatorial process

MEALY
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Translation into VHDL

• The FSM is described with one sequential process
  and one combinatorial process

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Translation into VHDL

• The FSM is described with one sequential process
  and one combinatorial process

MEALY
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Translation into VHDL

• The FSM is described with one sequential process
  and one combinatorial process

MEALY
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Translation into VHDL

• Complete and check the code
• Declare the signals and components
• Check and complete the sensitivity lists of ALL
  combinatorial processes with ALL signals that
  are
• used as condition in any IF or CASE statement
• being assigned to any other signal
• used in any operation with any other signal
• Check the sensitivity lists of ALL sequential
  processes that they
• contain ONLY one global clock and one global
  async. reset signal
• no other signals

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Other Good Ideas

• Keep things simple
• Partition the design (Divide et Impera)
• Example Start processing the next sample, while
  the previous result is waiting in the output
  register
• Just add a FIFO to at the output of you filter
• Do NOT try to optimize each Gate or FlipFlop
• Do not try to save cycles if not necessary
• VHDL code
• Is usually long and that is good !!
• Is just a representation of your block diagram
• Does not mind hierarchy