Scaling of MOS Circuits

1
Scaling of MOS Circuits

• EE213 VLSI Design

2
Scaling

• VLSI technology is constantly evolving towards
  smaller line widths
• Reduced feature size generally leads to
• better / faster performance
• More gate / chip
• More accurate description of modern technology is
  ULSI (ultra large scale integration

3
Scaling Factors

• In our discussions we will consider 2 scaling
  factors, a and ß
• 1/ ß is the scaling factor for VDD and oxide
  thickness D
• 1/ a is scaling factor for all other linear
  dimensions
• We will assume electric field is kept constant

4
Scaling Factors for Device Parameters

• Simple derivations showing the effects of scaling
  are derived in Pucknell and Eshraghian pages 125
  - 129
• It is important that you understand how the
  following parameters are effected by scaling
• Gate Area
• Gate Capacitance per unit area
• Gate Capacitance
• Charge in Channel
• Channel Resistance
• Transistor Delay
• Maximum Operating Frequency
• Transistor Current
• Switching Energy
• Power Dissipation Per Gate (Static and Dynamic)
• Power Dissipation Per Unit Area
• Power - Speed Product

5
Scaling of Interconnects

• Resistance of track R L / wt
• R (scaled) (L / a) / ( (w/ a ) (t /a))
• R(scaled) aR
• therefore resistance increases with scaling

A
t
w
L
B
6
Scaling - Time Constant

• Time constant of track connected to gate,
• T R Cg
• T(scaled) a R (ß / a2) Cg (ß / a) RCg
• Let ß a, therefore T is unscaled!
• Therefore delays in tracks dont reduce with
  scaling
• Therefore as tracks get proportionately larger,
  effect gets worse
• Cross talk between connections gets worse because
  of reduced spacing