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## Feedback: Principles

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Title: Feedback: Principles

1
Feedback Principles Analysis
Dr. John Choma, Jr. Professor of Electrical
Engineering University of Southern
California Department of Electrical
Engineering-Electrophysics University Park
Mail Code 0271 Los Angeles, California
90089-0271 213-740-4692 OFF 626-915-7503
HOME 626-915-0944 FAX johnc_at_almaak.usc.edu
(E-MAIL)
EE 448 Feedback Principles Analysis
Fall 2001
2
Overview Of Lecture
• Feedback
• System Representation
• System Analysis
• High Frequency Dynamics
• Open And Closed Loop Damping Factor
• Open And Closed Loop Undamped Natural Frequency
• Frequency Response
• Phase Margin
• High Speed Transient Dynamics
• Step Response
• Rise Time
• Settling Time
• Overshoot

65
3
Open Loop Model
• Gain
• Parameters
• ? Zero Frequency Gain
• ? Frequency Of Zero
• ? Frequency Of Dominant Pole
• ? Frequency Of NonDominant Pole
• Frequency Of Zero Can Be Positive (RHP Zero) Or
• Negative (LHP Zero)
• Note That A Simple Dominant Pole Model Is Not
Exploited
• Input And Output Variables
• Input Voltage Or Current Is X(s)
• Output Voltage Or Current Is Y(s)

3
66
4
Open Loop Transfer Function
(0)
• Damping Factor
• Measure Of Relative Stability
• Measure Of Step Response Overshoot And
Settling Time
• Undamped Natural Frequency
• Measure Of Steady State Bandwidth
• Measure Of "Ringing" Frequency And Settling
Time
• Poles
• Dominant Pole Implies
• Complex Poles Imply
• Identical Poles Imply

gtgt

1

lt

1

1
4
67
5
Closed Loop Transfer Function
• Loop Gain (Return Ratio w/r To Feedback
Factor, f )
• Closed Loop Gain

Obtained Through Substitution Of Open Loop Gain
Relationship Into Closed Loop Gain Expression

68
6
Closed Loop Parameters
(0)

• Closed Loop Damping Factor
• Closed Loop Undamped Frequency
• "DC" Closed Loop Gain
• T(0) Large For Intentional Feedback
• T(0) Possibly Large For Parasitic Feedback

(0)
?
(0)

69
7

• Damping Factor
• Potential Instability Increases With Diminishing
Damping Factor
• Potential Instability Strongly Aggravated By
Large Loop Gain
• Note Open Loop Damping Attenuation By Factor Of
• Square Root Of One Plus "DC"
Loop Gain
• For Intentional Feedback Having Closed Loop Gain
Of (1/f ),
• Worst Case Is Unity Gain (f
1), Corresponding To Maximal T(0)
• Open Loop Zero
• Closed Loop Damping Diminished, Thus Potential
Instability
• Aggravated, For Right Half
Plane Open Loop Zero
• Closed Loop Damping Increased, Thus Potential
Instability
• Diminished, For Left Half
Plane Open Loop Zero
• Undamped Frequency
• Measure Of Closed Loop Bandwidth
• Closed Loop Bandwidth Increases By Square Root
Of One Plus
• "DC" Loop Gain, In Contrast To
Increase By One Plus "DC" Loop
• Gain Predicted By Dominant Pole
Analysis

70
8
Step Response Example Of Damping Factor
Effect
Transmission Zero Assumed To Lie At Infinitely
Large Frequency

t

71
9
Phase Margin
(
v
• Unity Loop Gain Frequency
• Assumes Frequencies Of Zero And Second Pole Are
Larger Than
• Substitutions
• Phase Margin
• Difference Between Actual Loop Gain Phase Angle
And 180?
• A Safety Margin For Closed Loop
Stability
• Approximate Phase Margin
• Since Can Be Negative, k Can Be A Negative
Number
• Result Is Meaningful Only For

?
k

?

?
(k)

?
gt 1
72
10
Phase Margin Characteristic
Phase Margin (deg.)
120
100
T(0) 1
80
T(0) 5
60
40
20
T(0) 100
0
k
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
2.2
2.4
2.6
2.8
3
-20
-40
-60
73
11
Circuit Response Parameters

?

k
?

l Closed Loop Damping Factor l Closed Loop
Undamped Frequency l Phase Margin

?

?

?

?
(k)
74
12
Closed Loop Example Calculation
• Given
• Desire Maximally Flat Closed Loop Response,
Which
• Implies
• Computations
• Requisite Phase Margin
• In Practical Electronics, Phase Margins In The
60s Of Degrees
• Are Usually Mandated, Which Requires
That The Non-Dominant
• Pole Frequency Be 2.5 -To- 4 Times
Larger Than The Unity
• Gain Frequency

75
13
Closed Loop Step Response Problem
Formulation
• Problem Setup
• (Damped Frequency Of Oscillation)
• Normalized Variables
• (Normalized Time Variable)
• (Output Normalized
• (Error Between

• Output Responses)

?

?

?

?
t
(t)
?

(t)
?

(s)
?

76
14
Closed Loop Step Response Solution

(t)
• Solution
• Assumptions
• (Underdamped Closed Loop Response)
• (Satisfied For Right
Half Plane Zero)

?
t

?

?

?

lt 1
77
15
Closed Loop Step Response Example 1
M 1
78
16
Closed Loop Step Response Example 2
M 5
79
17
Closed Loop Settling Time

(x)
• Observations
• Magnitude Of Error Term Decreases Monotonically
With x
• Maxima Of Error Determined By Setting
Derivative Of Error
• Term With Respect To x To Zero
• Maxima Are Periodic With Period ?
• First Maximum Of Error Establishes Undershoot
Point
• Determine Second Maximum And Constrain To
Desired Minimal Error
• Procedure
• Let Be The Normalized Time Corresponding
To Second
• Error Maximum
• Let Be The Magnitude Of Error
Corresponding To
• If Is The Desired Settling Error,
Represents The Settling Time
• Of the Circuit

x
80
18
Closed Loop Settling Time Results

(x)
• Results
• For Large M (Far Right Half Plane Zero)

?

?

?

81
19
Closed Loop Settling Time Example
• Requirements
• Settling To Within One Percent In 1 nSEC
• Assume Zero Is In Far Right Half Plane
(Reasonable
• Approximation For Common Gate And
Compensated Source
• Follower First Order Approximation For
Common Source)
• Assume Very Large "DC" Loop Gain
• Computations
• Second Pole Must Be At Least 2.7 Times
Larger Than
• Unity Gain Frequency

?

?
0.01
?

gt
2.73

?
5.575
?

?
(887.2 MHz)

?

?

?
(537 MHz)
?

?
) 69.9

82