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Digital%20System%20Design%20Course%20Introduction

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Digital System Design Course Introduction Lecturer Date 2005/2/25 – PowerPoint PPT presentation

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Title: Digital%20System%20Design%20Course%20Introduction


1
Digital System Design Course Introduction
  • Lecturer???
  • Date2005/2/25

2
Contexts
  • Digital system design plays an important role in
    implementing digital functions in modern
    system-on-chip (SOC) design.
  • In this course, we will focus on developing the
    design skills for undergraduate students so that
    they can be familiar with state-of-the-art
    digital front-end design skills and design flow.

3
This course covers
  • Firstly, we will introduce the Hardware
    Description Language (HDL). The chosen HDL is
    Verilog. We will formally cover
  • The HDL grammar
  • The coding guideline
  • The synthesis guideline
  • Modern cell-based synthesis flow
  • Reuse Manual Methodology (RMM), 3rd ed.

4
This course covers
  • Secondly, we will ask students to design an
    advanced MIPS CPU based on the knowledge of
    Computer Organization and Design The Hardware /
    Software Interface, 3rd ed The assignment covers
  • Instruction set development.
  • HDL coding and simulation of major blocks such as
    Arithmetic Logic Unit (ALU) and Control Unit
    (CU).
  • Enhanced CPU design with pipelining and control
    of hazards
  • Integration of whole design using Verilog and
    perform simulation.
  • Evaluate your design using Design Analyzer
    (Synopsys).
  • Thirdly, port the MIPS CPU design to FPGA board
    and perform emulation use E1-304

5
Verilog HDL Outlines
  • Overview of Verilog Hardware Describe Languages
  • Modeling and Verification with Verilog-HDLs
  • Logic Design with Behavior Models
  • Introduction to synthesis with Verilog-HDLs
  • Synthesis of Combinational Circuits
  • Synthesis of Sequential Circuits
  • State machines Datapath Controllers
  • Architecture and Algorithm
  • Coding Style

6
Advanced MIPS CPU Outlines
  • Covered in Computer Architecture already. Just
    a brief review
  • Overview of MIPS CPU Architecture
  • Instruction Sets
  • Arithmetic Logic Unit Design
  • Control Flow Design
  • Pipelining Architecture
  • Forwarding Architecture

7
Last Year, Their Final Projects
  • From single-cycle design to pipelined,
    hazard-controlled MIPS CPU
  • Assembler/Compiler for MIPS R2000 instruction set
  • Demo with running a sorting algorithm

8
In This Semester, The Final Project
  • Design a synthsizable, pipelined,
    hazard-controlled MIPS machine using Verilog HDL
  • This machine implements specified basic
    instruction set of MIPS R2000, and you may add
    more instructions freely.
  • Performance/Area will be evaluate as one bonus
    for your final project.

9
Course Schedule
10
??????
11
???? (PC, ???,?????)
12
??????
13
?????
14
?????
15
IP Reuse and Coding guideline
16
SoC System on Chip
  • System
  • A collection of all kinds of components
    and/or subsystems that are appropriately
    interconnected to perform the specified functions
    for end users.
  • A SoC design is a product creation process
    which
  • Starts at identifying the end-user needs
  • Ends at delivering a product with enough
    functional satisfaction to overcome the payment
    from the end-user

17
SoC Definition
  • Complex IC that integrates the major functional
    elements of a complete end-product into a single
    chip or chipset
  • The SoC design typically incorporates
  • Programmable processor
  • On-chip memory
  • HW accelerating function units (DSP)
  • Peripheral interfaces (GPIO and AMS blocks)
  • Embedded software

Source Surviving the SoC revolution A Guide
to Platform-based Design, Henry Chang et al,
Kluwer Academic Publishers, 1999
18
SoC Example
19
SoC Architecture
20
TI OMAP5910 Dual-Core Processor
21
SoC??????
22
Engineering Productivity Gap
  • Engineering productivity has not been keeping up
    with silicon gate capacity for several years.
  • Companies have been using larger design teams,
    making engineers work longer hours, etc., but
    clearly the limit is being reached.

23
Why must IP Reuse?
Design productivity crisis Divergence of
potential design complexity and designer
productivity
24
Productivity of IP Reusing
2000
25
Reuse Methodology Manual (RMM)
  • Promoted by Synopsys and Mentor Graphics
  • Purpose of the RMM
  • Allow developers to consistently produce
    high-quality, reusable macros
  • Provide integrators with insights into how to
    select qualified IP
  • Integrate IP into System-on-Chip (SOC) designs
  • Broadly accepted by SoC Industry

26
Outline of the RMM
  • The overview of the SoC development flow
  • The process required for developing soft macros
  • The process of creating hard macros
  • The process of using IP in an SoC design
  • Conclude with several sections on more focused
    topics

27
Soft IP Configurable and Portable IP
  • Soft macro deliverables
  • Documentation
  • RTL code, both Verilog and VHDL
  • Synthesis scripts that work for a variety of
    technology libraries
  • Models and testbenches for verifying the macro in
    the chip environment
  • Installation scripts

28
Creation of the Deliverables
-Physical design issues -Timing and synthesis
issues -Functional design issues -Verification
strategies -Manufacturing test
-Clocking, registers and avoiding accidental
latches -Partitioning -VHDL Specific
Guidelines -Verification of compliance
Key Idea
Design Guidelines
Coding Guidelines
Simple, regular structures are easier to
get functionally correct, to verify,
and to synthesize
Synthesis Guidelines
Verification Methodology
-Based on a bottom-up synthesis strategy -A
robust set of timing budgets
-Simulation -Silicon prototyping
Productization
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