Digital System Design 1

1
Digital System Design 1

• Machine Organization and Hardware Programs

2
Outline of the Chapter

• Start the process of developing hardware
  implementation of RIC.
• Design will be in the form of hardware
  description using AHPL
• Complete the details of RIC architecture.
• After completing AHPL description of RIC a
  simple computer, larger and more complex computer
  systems can be designed.

3
Basic Organization of RIC

• 4 Operating Registers (Registers that Programmer
  has direct access to)
• AC accumulator
• IX index register
• SP stack pointer
• SR status register
• 1 Non-Operating Register (Do not have
  instructions to load and store into PC register).
• PC Program Counter.
• 3 Additional Registers not mentioned before
• IR Instruction Register
• Whenever a new instruction is fetched, it moves
  from memory to IR, where it is available for
  decoding. It is not considered Operating register
  since no instructions are provided to load or
  store data in it.
• MA Memory Address Register
• During memory read/write cycle the address of
  memory location first loaded into MA register.
• MD Memory Data Register
• Memory Read Cycle
• Address of desired Memory Word is first loaded
  into MA,
• Word stored at that Memory location is read in
  MD.
• Operation can be performed accessing this data.
• Memory Write Cycle
• Address of desired Memory location is first
  loaded into MA,

4
Register Interconnection and ALU

• Given the instruction set and the set of
  registers specification of Arithmetic Logic Unit
  (ALU) operations and register interconnections is
  required that would carry out those instructions.
• Given instruction set presented earlier it can be
  anticipated that ALU will include
• Adder
• Complementing Logic
• AND, OR and XOR logic
• Shift and Rotate logic
• Because instruction set include 32-bit arithmetic
  and logical operators, the ALU must have two
  32-bit inputs and one 32-bit output.
• Execution of instruction such as AND, ADD will
  require that AC be connected to one ALU input and
  MD to the other.
• If same adders is going to be used for INDEXING,
  IR register needs to be connected to one of ALU
  inputs and IX to the other.
• Branch and Stack instructions require connection
  of PC and SP to ALU.

5
BUSSES

• When a number of registers need to be connected
  to one or more targets, or
• It is desired to use on Combinational Logic Unit
  with several sets of arguments, buses are
  appropriate solution.
• ABUS BBUS will be used to provide for
  interconnections between the two ALU inputs and
  the various registers.
• OBUS is used to route output of ALU to any of
  registers.
• Three-bus structure is almost standard in
  computers and is a derivative of a natural
  requirement to perform operations that combine
  two operands to produce a single result.
• There is one more bus, carry input to the ALU,
  cin, which is effectively a 1-bit bus supplying a
  third argument to the adder within the ALU.
  Several possible sources may be connected to cin.
• Interconnection structure RIC registers and ALU
  is depicted in the following slide.

6
CPU and MEMORY

• CPU must be able to
• Send addresses and data to the memory, and
• Receive data from memory
• Addresses will normally pass through MA register.
• An additional BUS is conveniently specified,
  ADBUS, to provide address path between the CPU
  module and the memory module.
• Bi-directional data bus, DBUS, is provided as
  data bath between CPU and Memory.
• During read cycle, the memory module will connect
  the desired data to the DBUS, which in turn can
  be clocked into the argument register, MD.
• Note that SR (status register) is not shown in
  the following diagram of RIC.

7
Basic Organization of RIC

MEMORY
ADBUS
DBUS
MA
IR
MD
PC
AC
IX
SP
BBUS
ABUS
ALU
cin
OBUS
8
Register Transfers

• The execution of an instruction by a computer
  consists of a series of
• Transfers of data from register to register,
• Data being processed by ALU as required.
• Typically several such register transfers will be
  required to accomplish a single machine language
  insruction (e.g., MVT).
• When registers are interconnected by BUSES, the
  execution of a single register transfer requires
  the generation of several control signals to
  connect the various buses and registers.
• In RIC architecture signals must be generated to
  determine which
• Registers are placed on the buses, and
• ALU output is gated into which register.
• For example a basic operation is the AND
  transfer, in which the contents of MD and AC are
  AND-ed and the result is placed in AC. The
  control signals and interconnections involved in
  this transfer are depicted in following figure of
  the next slide.

9
Example of Control Signals AND transfer
10
AHPL Syntax of Bus Transfer

• Actual Description of BUS transfer of the
  previous (AND Operation) example is
• ABUS MD BBUS AC
• OBUS ABUS ? BBUS AC ? OBUS
• Abbreviated AHPL syntax of Bus Transfer. It
  applies only in the case of single, unconditional
  transfers, where there generally is no ambiguity
  in determining the bus connections.
• AC ? AC ? MD
• Care must be taken not to specify imposible
  connections like
• AC ? AC ? IX

11
Memory Read and Write AHPL Statements

• It will be assumed that memory
• Read operations are synchronous and that a memory
  word will be available at the same clock cycle in
  which the address is placed on ADBUS and the
  control line, read, is set to 1.
• ADBUS MA read 1 MD ? DBUS
• Write operations are likewise synchronous and
  that they will be carried out in same clock
  cycle, provided that write line is set to 1 at
  the same time as the address is placed on ADBUS
  and the word to be written is placed on DBUS.
• ADBUS MA write 1 DBUS MD
• Note that these statements do not describe the
  actual operations in the memory module. In the
  description (AHPL) of one module it can not be
  specified what happens in the other module. A
  complete system description will also include
  description of MEMORY module that is consistent
  with the assumptions made.

12
Fetch and Address Cycles

• Ready for the first step in designing of a
  Control Unit for RIC, that is for writing of a
  control sequence.
• Control Sequence is an AHPL program consiting of
  routines that execute RIC instructions.
• The complete sequence of operations required to
  carry out a single instruction will be referred
  to as an instruction cycle.
• Each instruction cycle will consist of at least
  two parts
• Fetch Cycle, and
• Execute Cycle.
• If the instruction includes an address, there
  will e one more part
• Address Cycle.

13
Fetch Cycle

• During the fetch cycle,
• The contents of the program counter, PC , are
  first shifted to memory address register, MA.
• Program counter, PC, is incremented in
  preparation for the next instruction fetch.
• Memory executes a read operation, placing the
  addressed word in MD register.
• The instruction is then transferred from MD to IR
  (to be decoded).
• Those steps are common to all instructions and
  are shown in following AHPL code
• MA ? PC.
• ADBUS MA read 1 MD ? DBUS PC INC(PC).
• IR ? MD.
• Note that there are two separate operations in
  step 2. This is possible because the read from
  memory operation does not use the internal bus
  structure.

14
Decoding Fetched Instruction

• Instruction after being fetched is now in IR
  register. However, first thing that is needed is
  to determine what kind of instruction it is
  32-bit or 2x 16-bin instructions. Recall that bit
  4 of the instruction specifies if it is 32-bit
  or 16-bit instruction.

15
Decoding Fetched Instruction (2)

• Following Branch instruction determines if
  instruction is a 32 or 16-bi instruction
• ? (IR4)/(16-bit instruction sequence).
• If control reaches step 5 the instruction is
  identified as 32-bit instruction. However, there
  are two basic types of instructions
• Branch Instructions
• 16-bit opcode and
• 16-bit displacement.
• All other instructions
• 8-bit opcode, and
• 24-bit address.
• Note that opcode IR030111 specifies the
  branch instructions. Thus testing for these bits
  we can branch to a sequence to implement branch
  instruction
• NO DELAY

16
Address Cycle

• If control reaches step 6, that specifies that
  the instruction is a 32-bit instruction with
  address. Therefore, address cycle can be started
  with this step with one exception. The exception
  is the case of immediate addressing whereby the
  address is really not an address rather it is an
  operand.
• Recall the table specifying addressing modes in
  RIC

AM Bits 5-7 Addressing Mode Mnemonic
000 Direct MVT ADDR
001 Indirect MVT (ADDR)
010 Indexed MVT ADDR, X
011 Indirect Indexed MVT (ADDR), X
100 Immediate MVT ADDR
17
Address Cycle (2)

• Immediate Addressing If bit 5, IR5, is 1 that
  indicates that the instruction uses immediate
  addressing. Step 6 tests if this is not the case
  then the sequence skips step 7, otherwise
  immediate addressing is executed by sign
  extending the data.
• NO DELAY? (IR5)/(8).
• MD07 ? (8 ? 0) ? MD8? (22).

18
Address Cycle (3)

• Address Mode Determination.
• Step 8 tests for indirect addressing
• NO DELAY(IR7)/(11).
• If IR7 1, then the indirect addressing cycle
  is entered at step 9, which moves the address
  portion of the instruction fro MD to MA. The
  address could just as well have been taken form
  IR, MD was used for consistency with later steps.
  Step 10 then reads the indirect address to MD.
• MA ? MD83
• ADBUS MA read 1 MD ? DBUS

19
Address Cycle (4)

• Step 11 in following AHPL code delivers the
  effective address, that is the actual address
  that will be used to access the operand, to MA.
• This step could have been broken up into several
  steps, however, conditional transfer was used to
  shorten the sequence.
• If IR6 0, the address is moved directly from
  MD to MA.
• If IR6 1, the address is indexed before being
  moved to MA.
• MA ? (MD831 ! ADD124(MD831 IX))
  (IR6, IR6)
• Start of execute cycle.

20
Example 6.1

• Rewrite step 11 making the bus connections
  explicit
• MA ? (MD831 ! ADD124(MD831 IX))
  (IR6, IR6)
• Solution
• Using Figure in slide 7 as reference MD and IX
  registers are routed to the adder through the
  ABUS and BBUS respectively. Since there is no
  carry input cin must be connected to zero.
• ABUS MD BBUS (8 ? 0),IX cin ? 0OBUS
  (ABUS ! ADD124(ABUS BBUS cin)) (IR6,
  IR6)MA ? OBUS831.

21
Execute Cycles for Addressed Instructions

• In step 12 the instruction will be on of 15
  addressed instructions to execute, with the
  effective address to be used in the instruction
  in MA.
• One way to resolve those 15 cases is to have 15
  way branch to separate sequences for each of the
  instructions.
• More common approach is to divide the
  instructions into categories based on various
  common features.
• To implement various branches, we first need to
  know the specific opcodes for the various
  instructions. The list of opcodes is given in the
  following table

22
Opcodes for Addressed Instructions
Operation Opcode (IR03)
SBC 0000
SUB 0001
ADC 0100
ADD 0101
ORA 1000
AND 1001
XOR 1010
MVT 0010
MVF 0110
CMP 0011
BIT 1011
INC 1100
DEC 1101
JSR 1110
JMP 1111

23
Execute Cycles for Addressed Instructions

• From other instructions we separate JMP and JSR,
  for which the address is not used to access
  memory but is transferred to PC as the address of
  the next instruction.
• Recalling that step 5 separated opcode 0111 for
  the branch sequence, it suffices to check for
  IR13 111 to identify JMP command.
• NO DELAY? (?/IR13)/(14).
• PC ? MA ? (1).

24
Execute Cycles for Addressed Instructions

• Step 13 executes JMP by transferring the
  effective address to PC and branching back to
  step 1 to fetch the new instruction.
• If the instruction is not a JMP, control branches
  to step 14. At this step control separates for
  execution of the JSR instruction. The final
  subroutine address (after possible indexing or
  indirect addressing) was stored by step 9 in MA.
• Before control is transferred to step 32 for
  execution of JSR, step 15 moves this address to
  IR831 sot that MA is free for addressing the
  stack in the process of saving the current
  contents of PC.
• NO DELAY? (?/IR02)/(16).
• IR831 ? MA to JSR ? (32).

25
Execute Cycles for Addressed Instructions

• The logic implementing this last branch decision
  takes advantage of the fact that the values of
  IR03 specifying JMP are now dont cares (they
  have been covered previously) as those for BRA.
  Since JSR instruction involves the stack, we
  shall defer further discussion of this
  instruction until later, when stack operations
  are covered.
• Once control reaches step 16, it is known that
  the address formed in MA will be used to access
  memory. All instructions, except MVF, start by
  reading memory, so a branch is specified at this
  step to separate MVF.
• NO DELAY? (IR0?IR2)/(19).
• MD ? AC
• write 1 ADBUS MA DBUS MD ? (1).
• Step 16 branches to step 19 if the command is not
  MVF,
• Steps 17 and 18 execute MVF by moving the
  contents of AC to MD and then writing them to
  memory.

26
Execute Cycles for Addressed Instructions

• Step 19 brings the operand to MD.
• ABUS MA MD ? DBUS read 1 ?
  (IR0?IR1)/(22).
• At step 19, the hardware control process is ready
  to execute any of the 13 instructions involving
  an operand from memory, of which 11 involve the
  accumulator.
• Separated for execution by step 20 are the two
  instruction that do not use the accumulator, INC
  and DEC. The implementation of step 19 takes
  advantage of the fact that the value of IR03
  specifying JMP and JSR are covered previously
  (e.g., are dont care).
• MD ? (INC(MD) ! DEC(MD)) (IR3, IR3)zff ?
  ?/OBUS nff ? OBUS0.
• write 1 ADBUS MA DBUS MD? (1).

27
Execution of an Instruction

• Operands are in AC MD Register
• Operation is performed by ALU as determined by
  opcode.
• Result is placed on OBUS, and
• Data is routed back to AC with exception of CMP
  and BIT operations.
• Important Note
• Operand in MD is obtained in an unique way
  depending on addressing mode applied (immediate,
  direct, indirect, indexed, indirect indexed).

28
Execution of an Instruction

• ALU consists of
• A set of logic units that perform operations
• ADD
• AND
• OR
• XOR
• ABUS and BBUS are permanently connected to the
  inputs of those units.
• Connections to those buses, and
• Connections to the appropriate ALU output to the
  OBUS is determined by the operation to be
  executed.

29
ALU Operations defined by 32-Bit Instruction set

• ADD ADD(ABUS, BBUS, cin)

Operation ABUS BBUS OBUS cin
ADD MD AC ADD 0
ADC MD AC ADD cff
SUB MD AC ADD 1
SBC MD AC ADD cff
MVT MD X ABUS X
ORA MD AC ABUS?BBUS X
AND MD AC ABUS?BBUS X
XOR MD AC ABUS?BBUS X
BIT MD AC ABUS?BBUS X
CMP MD AC ADD 1
30
Karnough Map of Instructions Opcode

• From Table in slide 22, (Table 6.3 in the book)

IR01 IR23 00 01 11 10
00 SBC ADC INC ORA
01 SUB ADD DEC AND
11 CMP BRA JMP BIT
10 MVT MVF JSP XOR
31
Connection Control to ALU

• ABUS MD vs. MD
• ABUS (MD, MD)((IR0? IR1)?
  (IR2?IR3), (IR0? IR1)?
  (IR2?IR3))

IR01 IR23 00 01 11 10
00 SBC ADC INC ORA
01 SUB ADD DEC AND
11 CMP BRA JMP BIT
10 MVT MVF JSP XOR
32
Connection Control to ALU

• BBUS
• BBUS AC
• cin (cff?IR3)?(IR1?IR3)

IR01 IR23 00 01 11 10
00 cff cff X x
01 1 0 X X
11 1 X X X
10 x X x X
33
Connection Control to OBUS

• ADD - Operation
• OBUS ADD(ABUSBBUScin) (IR0?IR2)?(IR
  0?IR3)

IR01 IR23 00 01 11 10
00 SBC ADC INC ORA
01 SUB ADD DEC AND
11 CMP BRA JMP BIT
10 MVT MVF JSP XOR
34
Connection Control to OBUS

• AND - Operation
• OBUS (ABUS?BBUS)(IR0?IR3)

IR01 IR23 00 01 11 10
00 SBC ADC INC ORA
01 SUB ADD DEC AND
11 CMP BRA JMP BIT
10 MVT MVF JSP XOR
35
Connection Control to OBUS

• OR - Operation
• OBUS (ABUS?BBUS)(IR0?IR2?IR3)

IR01 IR23 00 01 11 10
00 SBC ADC INC ORA
01 SUB ADD DEC AND
11 CMP BRA JMP BIT
10 MVT MVF JSP XOR
36
Connection Control to OBUS

• XOR - Operation
• OBUS (ABUS?BBUS)(IR0?IR2?IR3)

IR01 IR23 00 01 11 10
00 SBC ADC INC ORA
01 SUB ADD DEC AND
11 CMP BRA JMP BIT
10 MVT MVF JSP XOR
37
Connection Control to OBUS

• ABUS - Connection
• OBUS (ABUS)(IR0?IR2?IR3)

IR01 IR23 00 01 11 10
00 SBC ADC INC ORA
01 SUB ADD DEC AND
11 CMP BRA JMP BIT
10 MVT MVF JSP XOR
38
OBUS Clocking

• Content of OBUS gets transferred to AC with
  exception of CMP and BIT operations.
• AC(IR2?IR3) ? OBUS

IR01 IR23 00 01 11 10
00 SBC ADC INC ORA
01 SUB ADD DEC AND
11 CMP BRA JMP BIT
10 MVT MVF JSP XOR
39
Carry Flag

• Carry flag, cff, is affected only by four add and
  subtract operations as well as INC and DEC.
• cff(IR3?(IR1?IR0)) ? ADD0(ABUSBBUScin
  )

IR01 IR23 00 01 11 10
00 SBC ADC INC ORA
01 SUB ADD DEC AND
11 CMP BRA JMP BIT
10 MVT MVF JSP XOR
40
Zero and Negative Flag

• Zero flag is set when all bits in the bus are
  zero.
• zff ? (?/OBUS)
• Negative flag, nff, is set when sign bit
  (OBUS0) is 1.
• nff ? (OBUS0)
• Overflow flag, vff, is set when the sign of two
  operands is are the same but the sing of the
  result is different. This flag is affected with
  the same operations as cff. Note that buses are
  32 bit while output of ALU is 33 bit.
• vff(IR3?(IR1?IR0)) ? (ABUS0?BBUS0
  ?(ADD1(ABUSBBUScin))) (ABUS0?BBUS0?
  (ADD1(ABUSBBUScin)))

41
Putting it all Together

• ABUS (MD, MD) ((IR0? IR1)?
  (IR2?IR3), (IR0? IR1)?
  (IR2?IR3))
• BBUS AC
• cin (cff?IR3)?(IR1?IR3)
• OBUS ADD(ABUSBBUScin) (IR0?IR2)?(IR
  0?IR3)
• OBUS (ABUS?BBUS)(IR0?IR3)
• OBUS (ABUS?BBUS)(IR0?IR2?IR3)
• OBUS (ABUS?BBUS)(IR0?IR2?IR3)
• OBUS (ABUS)(IR0?IR2?IR3)
• AC(IR2?IR3) ? OBUS
• cff(IR3?(IR1?IR0)) ? ADD0(ABUSBBUSci
  n)
• zff ? (?/OBUS)
• nff ? (OBUS0)
• vff(IR3?(IR1?IR0)) ? (ABUS0?BBUS0
  ?(ADD1(ABUSBBUScin))) ? (ABUS0?BBUS0?
  (ADD1(ABUSBBUScin)))
• ? (1).

42
Register Only (16-bit) Instructions

• 16-bit instructions have IR4 0
• Step 4 in control sequence branches to handle
  those instructions.
• Packing two 16-bit instructions in one fetch
  cycle is necessary otherwise there is no
  advantage of using this feature.
• When 2 16-bit instructions are fetched
• Upper 16-bits will be processed first in the same
  manner as the 32-bit instruction.
• Instead of going back to fetch another
  instruction the next instruction is processed.
• There are two ways that this can be accomplished
  (e.g. processing second 16 bit instruction)
• Performing decoding in place this solution
  implies extra hardware to accomplish it.
• Shifting upper 16-bits to lower half of 32-bit
  Word this solution uses the same hardware to
  decode the instruction with added expense of
  shifting.
• RIC uses 2nd solution.
• To keep track of upper/lower half of each 16-bit
  instruction a second half flag, shf, is used. Se
  the flow chart bellow

43
Register Only (16-bit) Instructions

• Fetch Sequence for 16-bit Instructions

1-3
FETCH INST. shf ? 0
4
Yes
16-BIT
No
5-49
Execute 32-BIT
50-99
Execute 32-BIT
100
1
shf
0
101
IR015 ? IR1631 shf ? 1
44
Interpretation of 16-bit Instructions

• Separate Register-Only instructions from the
  rest.
• Register only instructions all operations listed
  in Table presented in the next slide (Fig 6.8. in
  the book).
• Note that opcode is identical to 32-bit
  instructions (no additional decoding hardware
  required) with exception of MVF that was replaced
  by shift/rotate instruction.
• In addition format of 16-bit instruction is
  repeated for convenience.
• Let RFN(AD1) and RFN(AD2) represent the registers
  specified by AD1 and AD2 respectively.
• Two operand instructions (ADD, AND) can be
  generalized as
• RFN(AD1) ? RFN(AD1) ? RFN(AD2)
• ? stands for logical or arithmetic operation as
  specified by opcode.
• Example MVT will be
• RFN(AD1) ? RFN(AD2)
• Since AD1 and AD2 can both specify any register,
  there is no need for the MVF. Its opcode is used
  for shift/rotate instruction.

45
Register Only 16-bit Instructions

• 16-bit Register Only Instructions

Operation Opcode (IR03)
SBC 0000
SUB 0001
ADC 0100
ADD 0101
ORA 1000
AND 1001
XOR 1010
MVT 0010
Shift/Rotate 0110
CMP 0011
BIT 1011
46
Two-Address Instruction Format

00 Register Mode 10 Immediate Quick (IMQ)
gt AD2 4-bit Immediate Operand
47
Register Only 16-Bit Instructions

• It was noted earlier that RIC architecture will
  not permit direct execution of an operation such
  as
• AC ? AC ? IX AC and IX registers are both on the
  BBUS.
• Desired result can be achieved by first routing
  the contents of the register specified by
  RFN(AD2) to MD (which is connected to ABUS).
• Also, immediate quick (IMQ) operand is in
  register specified by AD2. This instruction is in
  IR register. IR register is also connected to
  ABUS.
• Thus, for two-operand instructions, AD1 will
  specify the operand that is on BBUS while AD2
  will specify the operand on ABUS.
• To understand branches of AHPL code, map of
  opcodes for register-only instructions is
  depicted.

48
Register Only 16-Bit Instructions

• Opcodes for Register-Only Instructions
• Note opcodes with IR01 11 are not used, thus
  can be treated as dont cares. Also it will be
  assumed that Opcode 0111 will not be used thus it
  can be treated as dont care.

IR01 IR23 00 01 11 10
00 SBC ADC ORA
01 SUB ADD AND
11 CMP BIT
10 MVT SH/ROT XOR
49
Register Only 16-Bit Instructions

• The first branch of the 16-bit sequence will be
• ? (IR0 ? IR1)/(other 16 bit instruction)
• Shift/Rotate Sequence may be written as follows
• NO DELAY ? (IR1 ? IR2)/(Shift/Rotate)

50
Shift/Rotate

• (IR1 ? IR2)

IR01 IR23 00 01 11 10
00 SBC ADC ORA
01 SUB ADD AND
11 CMP BIT
10 MVT SH/ROT XOR
51
Beginning of Execution of Register Only
Instructions

• Move Operand specified by AD2 to MD.
• High order 8-bit vectors moved with IR to MD
  made necessary by sign extension.
• BBUS831 (AC831 ! IX ! SP) (IR12,
  IR12? IR13, IR12?IR13)BBUS07 (8 ?
  0 ! AC07)(IR12?IR12)ABUS027 (28 ?
  0 ! (28 ? 0))(IR12?IR12)ABUS2831
  IR1215OBUS027 (ABUS !
  BBUS)(IR10?IR10)MD ? OBUS

52
Execution of 16-bit Register-only Instructions

• ABUS (MD, MD) ((IR0? IR1)?
  (IR2?IR3), (IR0? IR1)?
  (IR2?IR3))
• BBUS (AC ! 8 ? 0! IX! 8 ? 0! SP) (IR6,
  IR6?IR7, IR6?IR7)
• cin (cff?IR3)?(IR1?IR3)
• OBUS (ADD(ABUSBBUScin) ! (ABUS?BBUS) !
  (ABUS?BBUS) ! (ABUS?BBUS) ! (ABUS))
  ((IR0?IR2)?(IR0?IR3) ! (IR0?IR3) !
  (IR0?IR2?IR3) ! (IR0?IR2?IR3) !
  (IR0?IR2?IR3))
• AC(IR6?(IR2?IR3)) ? OBUS
• (SP ! IX)((IR6? IR7?(IR2?IR3)), IR7)
  ? OBUS831
• cff(IR3?(IR1?IR0)) ? ADD0(ABUSBBUScin
  )
• zff ? (?/OBUS)
• nff ? (OBUS0)
• vff(IR3?(IR1?IR0)) ? (ABUS0?BBUS0
  ?(ADD1(ABUSBBUScin))) ? (ABUS0?BBUS0?
  (ADD1(ABUSBBUScin)))
• ? (100).
• NO DELAY? (shf)/(1).
• IR015 ? IR1631 shf ? 1? (15).

53
Shift/Rotate Instruction

• Shift/Rotate Instruction is register only
  instruction.
• However
• No address is needed,
• It is available only on AC register.
• Format

54
Format of Shift/Rotate Instruction

0110
0
X
M
000
D
DISTANCE


Shift Distance 1-31 Bits
Shift 0 Rotate 1
55
Shift/Rotate Instruction

• Bits 0-4 establish that this is the 16-bit
  shift/rotate instruction.
• Shift if Bit 5 0, Rotate if Bit 5 1.
• Bit 10 Indicates the direction of shift or
  rotate.
• Bit 6 indicates whether or not the carry is
  included in rotates, or whether shifts are
  arithmetic or logical.
• There are 7 distinct operations
• LSR Logical Shift Right
• ASR Arithmetic Shift Right
• SHL Shift Left
• ROR Rotate Right
• RRC Rotate Right with Carry
• ROL Rotate Left
• RLC Rotate Left with Carry
• These 7 AHPL statements defining each operation
  can be combined into a single conditional
  transfer based on the controlling bits in the
  instruction.
• However, this provides only for 1 bit
  shift/rotate. There is 1 basic approaches to
  perform multiple shift/rotate
• Special logic for multiple shifts/rotates (will
  be investigated later), and
• Employ looping in the control sequence a
  simpler approach.

56
Shift/Rotate Instruction

• SHC is a shift counter
• SHC ? DEC(IR1115).
• AC0 ? (AC0!AC1!AC31!cff!0) (IR5?IR6
  ?IR10, IR10, IR5?IR6?IR10, IR5?I
  R6?IR10, IR5?IR6?IR10)AC130 ?
  (AC029!AC231) (IR10?IR10)AC31 ?
  (AC30!AC0!cff!0) IR10,
  IR5?IR6?IR10, IR5?IR6?IR10, I
  R5?IR10)cff(IR5?IR6) ?
  (AC31!AC0) (IR10?IR10) SHC ?
  DEC(SHC)(?/SHC,(?/SHC))/(61, 100).

57
Branch Commands

• Branch commands, in their simplest form, test one
  of the four flags for a specified condition.
• If condition is met then a branch is made to an
  instruction at a specified distance relative to
  the current instruction
• If not the next sequential instruction is
  executed.
• 8 Branch commands one for each possible value of
  the four flags as tabulated in the table in the
  following slide.

58
Branch Commands

Mnemonic Meaning Flag Conditions
BEQ Branch Z 1
BNE Branch on NOT equal to zero Z 0
BPL Branch on plus N 0
BMI Branch on minus N 1
BCS Branch on carry set C 1
BCC Branch on carry clear C 0
BVS Branch on overflow V 1
BVC Branch on no overflow V 0
BRA Branch always Any
BSR Branch to subroutine Any
59
Values of Flags after CMP command

• ? is an APL operator the encodes the binary
  number in MA to form a decimal integer. Although
  it is not in AHPL , it denotes inverse of ? AHPL
  operator.

Relative Values Signs Resulting Flags Resulting Flags Resulting Flags
AC Mlt?MAgt Z1 N0 V0
AC gt Mlt?MAgt Both Positive Z0 N0 V0
AC gt Mlt?MAgt Both Positive Z0 N0 V0
AC gt Mlt?MAgt AC pos, M neg, or Z0 N1 V1
AC gt Mlt?MAgt AC pos, M neg Z0 N0 V0
AC lt Mlt?MAgt Both Positive Z0 N1 V0
AC lt Mlt?MAgt Both Positive Z0 N1 V0
AC lt Mlt?MAgt AC pos, M neg, or Z0 N0 V1
AC lt Mlt?MAgt Z0 N1 V0
60
Karnaugh Map of Relative Magnitudes indicated by
Flags

• lt ? (N?V)?(N?V) (N ? V)
• ? Z

NV Z 00 01 11 10
0 gt lt gt lt
1 X X X
61
Boolean Expressions for Branch Functions

• Boolean Branch Expressions

Relative Values Logical Functions Branch Mnemonic
AC Mlt?MAgt Z BEQ
AC lt Mlt?MAgt N?V BLT
AC Mlt?MAgt Z?(N?V) BLE
AC Mlt?MAgt (N?V) BGE
AC gt Mlt?MAgt (Z?(N?V)) BGT
62
Format of Branch Instruction

• Displacement (16-bit) is treated a signed 2s
  complement number, thus permitting a branch range
  of 32K forward and backward.
• Conditions field (11-bit) will specify the
  conditions to be tested.
• Meaning of the Branch Instruction
• IF the branch conditions are satisfied
• THEN add displacement to the next sequential
  address to obtain
• the address of the next instruction
• ELSE the next sequential address will be the
  address of the next
• instruction.

63
Format of Branch Instruction

• ?((?/(IR715 ? (C,C,Z,Z,N,N,V,V,N?V))) ?
  IR6)/(1).

0111
1
CONDITIONS
Displacement
OPCODE
32-BIT
5
6
C
C
Z
Z
N
N
V
V
15
Branch-0BSR-1
N?V
Branch on0 Branch on1
64
Control Sequence of Branch Instructions

• NO DELAY ? (IR5)/(35).
• SP ? DEC(SP) MA ? SP.
• MD ? (8?0),PC
• ADBUS MA DBUS MD write 1.
• ABUS ((16?0),IR1631 ! (16?0),IR1631 !
  (8?0),IR831) ((IR 16?IR 0),
  (IR16?IR 0), IR0)BBUS (8?0),PCcin
  0 // JSROBUS (ABUS ! ADD132(ABUS
  BBUS cin)) (IR 0, IR 0)PC ?
  OBUS831 ? (1).

65
Special-Purpose Instructions

• PSH, POP, SEC, CLC, NOP, HLT and RTS are all
  16-Bit instructions (they do not requires
  address).
• IR01 11 was not used for 16-Bit
  instructions.
• Because there are so few special-purpose
  instructions they could have been fit in 8-bit
  length instruction. However, complication is
  getting a hardware to interpret yet another
  instruction length would have not been worth it.
• 16-Bit instructions that start with IR0111
  will be divided into four categories as shown in
  following map.

66
Special-Purpose Instructions

• Categories of 16-bit special purpose
  instructions

IR01 IR23 00 01 11 10
00 SBC ADC SYS ORA
01 SUB ADD IOT AND
11 CMP SUPV BIT
10 MVT SH/ROT MISC XOR
67
Special-Purpose Instructions

• SYS - System Instructions Category
• Includes instructions that affect the general
  operating state of the system without
  manipulating data or modifying registers.
• HLT, NOP
• IOT Input/Output and Interrupt Category
• Includes all instructions specifically involving
• Input/Output operations
• System Interrupt
• SUPV Supervisory Group Category
• Includes instructions specifically intended for
  use only by the machine operators or system
  programmers that are not available to ordinary
  users.
• MISC Miscellaneous Group Category
• Includes any instructions that do not fit in any
  other category.
• PSH, POP, SEC, CLC, RTS

68
Special-Purpose Instructions

• Each category will be allocated 4-bits allowing
  thus 16 instructions per category. Those
  additional opcode bits are placed in IR69.
• Opcodes are given in the table bellow

IR09 Instruction
1100 01 0000 NOP
1100 01 0001 HLT

1110 01 0000 CLC
1110 01 0001 SEC

1110 01 0100 PSH
1110 01 0101 POP
1110 01 0111 RTS
69
Special-Purpose Instructions

• NO DELAY ? (IR0 ? IR1)/(70).
• NO DELAY ? (DCD(IR23)/(71,110,130,170).
• NO DELAY // System Group ?
  (?/IR69)/(100). // NOP
• DEAD END. // HLT
• NO DELAY // MISC Group ? (DCD(IR67)/(131,1
  40,150,160).
• cff ? IR9 // CLC SEC ? (100).
• NO DELAY // PUSH, POP, RTS ?
  (IR9)/(144). // PUSH
• SP ? DEC(SP) MA ? SP.
• MD ? AC.
• ADBUS MA DBUS MD write 1 ? (100).
• MA ? SP.
• ADBUS MA MD DBUS read 1 SP ?
  INC(SP). // POP RTS
• AC IR8 ? MD // POPPC IR8 ?
  MD831 // RTS ? (100).

70
Options in Computer Structures

• In previous sections we have completed design of
  RIC in considerable detail.
• This AHPL description of the RIC system is not
  intended to imply that this is the only
  reasonable design or even a preferable design.
• Although RIC has many features in common with
  various real computers the number of possible
  variations and options in organization is
  virtually unlimited.
• In the following section the various possible
  options will be discussed.

71
Von Neumanns Organization

• Storage of Data and Program in the same form and
  in the same Random Access Memory. This implies
• Separation of Registers and Logic from Memory
• A Program Counter Instruction Register
• Input/Output Facilities.
• Fig 6.19 (a) illustrates essential features of a
  von Neumann structure.

72
Basic Von Neumann Organization

IR
RAMStoringInstructions and Data
Registersand Logic
IOT
PC
73
Basic Von Neumann Organization

• This Organization also implies the division of
  the instruction cycles into three basic parts as
  shown in the following figure.

1
Instruction Fetch
Impliedarguments
2
Accessingargumentsfrom memory
3
Execution ofInstructions
74
Basic Von Neumann Organization

• Available options with the von Neumann
  organization can be classified in terms of
  options in structuring the three blocks of
  previous figure.
• Number of options available in the instruction
  execution block is essentially unlimited.
• Some possible categories of instructions were
  discussed earlier (e.g., branch, arithmetic
  instructions, shift/rotate, logical instructions,
  etc. ).
• Next the options in the accessing of arguments
  will be the subject of discussion.

75
Instruction Stream

• The sequence of instruction fetches and executes
  is often called the instruction stream.
• The function of block 1 in the figure is to fetch
  each instruction in turn form the instruction
  stream and make it ready for execution.
• Within instruction fetch cycle there are
  essentially two types of options available.
• Manner in which the address of the next
  instruction is obtained.
• The number of words per instruction.

1
Instruction Fetch
Impliedarguments
2
Accessingargumentsfrom memory
3
Execution ofInstructions
76
Fetch Cycle

• Manner in which the address of the next
  instruction is obtained
• Include the address of the next instruction in
  each instruction.
• Instruction fetch requires moving the next
  instruction address from the instruction register
  to the memory address register and reading the
  new instruction into the instruction register.
  This option was employed in early computers.
• Standard techniques today is that used in RIC.
  The program is assumed to be stored in sequential
  locations in memory, and a program counter is
  used to keep track of the next instruction
  address. Branch instructions can change the next
  instruction address, but they do so by modifying
  the program counter so that the fetch cycle
  uniformly refers to the program counter for the
  instruction address.

77
Fetch Cycle

• The partial-word per instruction.
• Machines with longer words may pack two or more
  instructions in a word.
• Microprocessors may require several words per
  instruction.
• Basic structure of the fetch cycle for a machine
  with more than one instruction per words is shown
  if Fig. 6.20(a).
• If an instruction has m-bits, the usual technique
  is to execute the instruction in the most
  significant m-bits of the instruction register.
• After the fetch of an instruction words, each
  individual instruction must in turn be shifted
  into the correct position.
• Note If n number of instructions per word, n
  is not necessarily a constant for a given
  machine. that is some instructions may occupy a
  full word, others only part of word. In such
  cases the opcode will contain information to set
  the appropriate value of n as was done in RIC.
• n-number of instructions per word

• Fetch Cycles for partial-word

From previousInstruction
Kn?
No
Yes
K ? 1
Shift nextinstructioninto position
Fetch newinstructionword
K ? K1
PC ? INC(PC)
ExecuteInstruction
78
Fetch Cycle

• Multiple word instructions
• Number of words in the instruction will usually
  be specified in the first instruction word.
• If additional words are required, they are
  fetched from successive memory location until n
  words have been assembled into the instruction
  register.
• n-number of words per instruction

• Fetch cycles for multiple-word instructions

From previousInstruction
K ? 1
Fetch instructionword K
K ? K1
PC ? INC(PC)
Kn?
No
Yes
ExecuteInstruction
79
Fetch Cycle

• Example 6.2
• Write in AHPL the steps of the control sequence
  that specify the instruction fetch for a computer
  that employs a 12-bit 218-word RAM. Instructions
  that require an operand from memory must consist
  of 24 bits (i.e., two computer words).
  Instructions that do not require an argument from
  memory are 12-bit instructions. Bit IR0 0,
  for two-word instructions. For compactness memory
  reference may be expressed using BUSFN.
• Solution
• PC MA 18-bit registers
• IR 24-bit register
• MD is 12-bit register.
• First instruction is always placed in IR011.

• Solution
• MA ? PC.
• MD ? BUSFN(M, DCD(MA)).
• IR011 ? MD.
• ? (IR0)/(execution of one-word instructions).
• PC ? INC(PC) MA ? PC..
• MD ? BUSFN(M, DCD(MA)).
• IR1223 ? MD.
• Accessing of argument

80
Addressing Options

• Options available in accessing of arguments in
  block 2 of Fig 6.19(b).
• Arguments are used in a very broad sense it
  includes
• Operands to be processed.
• Results to be stored, and
• Addresses for Branch operations.
• Every instruction requires access to at least one
  argument.
• Arguments may be broadly grouped into two
  classifications
• Addressed, and
• Implied.

81
Addressing Options

• Implied arguments
• They are the contests of registers whose use is
  specified by the opcode itself.
• For instance ADD and AND imply the
  accumulator as source of one operand and the
  destination of the result.
• Processing of the registers implied by the opcode
  automatically accesses these arguments.

82
Addressing Options

• Addressed arguments
• Registers are Memory devices.
• Memory in modern computers may include a whole
  hierarchy of devices rather than just one main
  memory.
• Memory is used in the basic von Neumann sense it
  denotes a separate section of the computer system
  consisting of 2n information storage locations,
  identified by n-bid addresses.
• An addressed argument requires the generation of
  an n-bit address, which is in some way specified
  by the instruction.
• This address and memory access is indicated as
  block 2 in Fig. 6.19 (b).
• The options available in this block are the
  subject of the reminder of this section.

83
Addressing Options

• 4 basic options for specifying addressing
• Number of Operands
• Number of Words or Bytes per Operand
• Number of access to memory to obtain operand
• Logical computation of addresses (e.g., indexing,
  referred addressing, etc.)

• Obtaining arguments from memory

Multiple
Single
One word per operand
Other
SINGLE INDIRECT
IMMEDIATE
RECURSIVE INDIRECT
DIRECT
84
Addressing Options

• How many arguments are to be accessed in memory
• Single vs. Multiple
• Single-address format one in which one argument
  is addressed and the others are implied. It is
  the most common form of addressing.
• Multiple-address instructions are often stored in
  several words, as discussed in previous section.
• Each options terminates with all possible
  addressing modes depicted at the bottom of the
  tree.
• Number of words per argument
• One word per operand (most machines)
• Multiple words in consecutive memory locations
  per operand. Instruction specifies location of
  first operand and the remaining of words are
  implied to be in consecutive locations as well as
  their number.
• Number of accesses to memory to obtain each
  operand (or each word of an operand).

85
Addressing Options

• Immediate Addressing
• Argument is part of the instruction so that no
  additional accesses to memory are required.
• Direct Addressing
• Requires one additional memory access.
• Single-level Indirect Addressing
• Requires two additional memory accesses.
• Recursive Indirect Addressing (not provided in
  RIC)
• Will allow any number of successive memory
  accesses before the operand is finally obtained.
  This is accomplished by replacing the indirect
  addressing specification bit as well as the
  address in IR after each successive memory
  access. The operand is not read form memory until
  a 0 in this bit position is encountered.
• Index Addressing (not depicted in the tree).
• Addressing is formed by adding the contents of an
  index register to a vector from IR. In general,
  addresses can be generated as combinational logic
  functions of any register or combinations of
  registers.
• Referred or Register Indirect Addressing
• Opcode is used to specify a register within the
  CPU that contains the address.

86
Addressing Options

• In some computers, an address of sufficient
  length to specify any word in the memory space
  may never appear in the instruction stream.
  However, a complete address might be formed by
  exercising some of the options in levels 3 and 4
  such as indirect addressing or referred
  addressing.
• Example when an indirect address cycle is
  executed in RIC, a full 32-bit word is fetched
  but only 24-bits are used. If RIC were to be
  modified to use full 32 bits, its address
  capacity would be increased to 232 4G words. To
  accomplish this, we must increase the size of MA
  and PC to full word length.
• This modification does not fully solve the
  problem because an address is still needed in the
  instruction, even with indirect addressing.
  Solution procedure
• During a fetch cycle, a full-length address
  (32-bits in RIC) is transferred from PC to MA and
  an instruction is fetched.
• During execution of an addressed instruction, a
  partial address (24 bits in RIC) is transferred
  to the corresponding position of MA and catenated
  to the most significant position (8 bits in RIC)
  left in MA by instruction fetch.
• When such a scheme is used is common to consider
  the memory as being divided into pages.
• The most significant portion of an address, which
  is not changed by direct addressing, is known as
  the page number.
• The least significant portion normally taken from
  the instruction, is known as the page address or
  page offset.
• The complete full-length address is know as the
  absolute address.

87
Addressing Options

• Example
• Consider a machine with 24-bit words, in which
  the standard single-address instruction consists
  of an 8-bit opcode and a 16-bit address.
• In such a case, the upper 8-bits of an absolute
  address would be the page number and the lower
  16-bits would be the page address
• 16M word address space is divided into 256 pages
  of 64K words each.
• The page number designated by the leading bits of
  PC is know as the current page.
• As long as direct addressing is used the program
  will be executed on the current page.
• Indirect addressing need not be used unless it is
  necessary to move off the current page.

88
Example 6.3

• Figure 6.22 shows the basic organization of a
  12-bit, 4K computer. Device an instruction format
  for addressed instructions and a page-addressing
  scheme. Also device a convenient mean to use
  memory locations to serve the function of index
  registers. Use only one word per instruction.

89
Example 6.3

• Solution
• 12 bits 3 bits for Opcode (minimum
  possible) 1 bit for indirect addressing 8
  bit max for page addressing
• 8 bit 4 bits gt 16 pages each 256 words, or
• 8 bit 5 bits gt 32 pages each 128 words.
• Instruction format for 12 bit computer

D/I 0 direct addressingD/I 1 indirect
addressing
Z/C 0 page 0Z/C 1 current page
90
Example 6.3

• With 8-bit page address, the direct addressing
  range would be 256 words 128 on page 0 and 128
  on the current page.
• Programming advantage
• Locations on page 0 can be pointers containing
  addresses of standard subroutines or tables of
  constants (e.g., Multiplication and Division
  subroutines). Programs (located anywhere in
  memory) could refer to these routines by an
  indirect reference through page 0.
• Indexing feature can be implemented efficiently
  by using standard memory locations of page 0. For
  example first 8 locations on page 0 (absolute
  address 000-007 hex) will be used as autoindex
  registers. When an indirect reference is made to
  these locations, the content will be
• Incremented by one and rewritten in the same
  location, and
• The incremented number will be used as the
  effective address.
• MVT I Z 4 // Z indicates page 0
• If the contents of location 004 were 163 hex, the
  above command would read from location 4 gt 163,
  increment that value to 164, 164 would be
  rewritten back to location 4, and the content of
  location 164 would be loaded into the
  accumulator.
• Provides convenient means to step through an
  array of data.

91
Addressing and Memory Organization Issues

• Paging
• Many 8 bit microprocessors use 16-bit addresses,
  providing 64K address space, fetched in 2 bytes
  from memory.
• It is common to consider the first byte as a page
  number and the second byte as page address, thus
  dividing the address space into 256 pages of 256
  words each.
• However, there is no use of indirect addressing
  to obtain addresses longer than can be obtained
  in an instruction, and no concept of current
  page.
• Base Addressing
• At least one base address register is needed.
• Whenever an argument is accessed in memory, a
  page address from IR is added to or concatenated
  with a base address register to form the absolute
  address.
• Transparent process to the programmer, however,
• Instruction for loading each base address
  register must be provided.
• Base addressing facilitates relocatability of the
  code, and
• Increases addressing capacity.

92
Example 6.4

• Relocatability through base addressing may be
  included in RIC by adding a 24-bit register,
  BASE, and making a few modifications in the
  control sequence.
• The BASE register may be cleared, saved, or
  loaded by adding this one additional register to
  the operand lists for the 16-bit two-operand
  instructions.
• The approach to implementing relocatability will
  assume that PC will at all times contain the
  actual address of the instruction to be executed.
  
• The base address must be added to every address
  used in the execution of an instruction that is,
  either a data address or the address of a next
  instruction for JMP or JSR.
• Identify and modify those parts of the RIC code
  to provide for adding BASE to any addresses used
  in the execution of an instruction.

93
Example 6.4

• Solution
• MA ? PC. // Same as before
• Changing how content of MA is obtained.
• BASE is connected to BBUS
• MA ? ADD(MD831,BASE).
• MA ? ADD(MD831,BASE)? (IR6)/(12).
• 11A MA ? ADD(MA,IX)
• Start of execute cycle.

94
Example 6.4

• The stack pointer SP is another register that
  must continuously contain an address in the area
  of the process execution. Unlike PC the stack
  pointer is accessible to and can be loaded by the
  user. It cannot therefore be assumed to contain a
  contain a relocated address. Each time the
  contest of SP is placed in MA, BASE register must
  be added. This will require step 32 to be
  modified as follows
• MA ? DEC(SP) SP ? DEC(SP)
• 32A MA ? ADD(MA,BASE)

95
Example 6.4

• Registers SP and BASE can not be added directly
  since they are connected to the same bus. Thus
  and identical modification must be made in step
  141 in the implementation of PSH. For POP and
  RTS, it is again necessary to replace the single
  step of AHPL sequence 144.
• Original sequence
• SP ? DEC(SP) MA ? SP.
• MD ? AC.
• ADBUS MA DBUS MD write 1 ? (100).
• MA ? SP.
• Modified sequence
• SP ? DEC(SP) MA ? SP.
• 141A MA ? ADD(MA,BASE)
• MD ? AC.
• ADBUS MA DBUS MD write 1 ? (100).
• MA ? SP.
• 144A MA ? ADD(MA,BASE)

96
Example 6.4

• If a single program is being executed this
  modification is simple in principle and will not
  cause any problems.
• Relocation through the use of a base register
  will usually be sued only in multiprogramming
  environment in which monitoring or executive
  software (typically part of OS) must control the
  switching from one program to another.
• All programs will be compiled or assembled using
  a standard starting address, START.
• When the monitor loads a program for execution it
  will choose an appropriate location based on the
  current operating situation. The displacement of
  the program location from START will be saved by
  the monitor in a location NEWPROG. The monitor
  itself will have a fixed location in memory
  starting at location MONITOR.

97
Multi-Cycle Instructions

• The memory reference instructions considered so
  far were executed by a single transfer of
  information from one register to another
  register.
• Some instructions however may require many
  consecutive register transfers.
• In general the approach to designing the control
  sequencing hardware will be the same regardless
  of instruction complexity.

98
Multi-Cycle Instructions

• Fixed Point Multiplication Example
• There are various possible approaches to the
  multiplication of the numbers that may be
  negative
• Negative Numbers may be stored as
• Twos complement, or
• Sign and Magnitude.
• More elaborate discussion of this topic is
  deferred until chapter 15.
• The simplest (not necessarily the fastest nor
  least expensive) approach to multiplication is
  keeping track of signs and multiplying the
  magnitudes.

99
Multi-Cycle Instructions

• Fixed-point multiplication of two 32-bit numbers
  may result in a 64-bit product, another register,
  the MQ register, must be added to store the 32
  least significant bits of the product.
• It will also be required to count number of bits
  of the multiplier that have been treated at any
  given stage in the process. For this reason a
  5-bit counter, designated SHC will be added.
• cff a 1-bit register will be used to store the
  sign.
• Hardware configuration is depicted in the Figure
  6.29 presented in the next slide.

100
Multi-Cycle Instructions

• Multiplication Hardware

101
Multi-Cycle Instructions

• Multiplication instruction is not included in
  RIC.
• Implement control sequence for fixed point
  multiplication as describe previously.
• Multiplier is in the AC from the previous
  instruction.
• Multiplicand has been just read from the memory
  and placed in MD.

102
Multi-Cycle Instructions

1. cff ? 0? (AC0)/(3).
2. AC ? ADD132(32 ? 0 AC 1) cff ? cff