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Package-Chip%20Co-Design

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... solutions Power integrity in package Design Constraints for IO Planning and Placement Power integrity Timing I/O standards ... design flow PCB ... EMI and SSN ... – PowerPoint PPT presentation

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Title: Package-Chip%20Co-Design


1
Package-Chip Co-Design
  • Prof. Lei He
  • Electrical Engineering Department, UCLA
  • LHE_at_ee.ucla.edu
  • http//eda.ee.ucla.edu

2
Outline
  • Overview of Chip Package Co-design
  • IO planning and placement
  • Power integrity in package
  • Reading package tutorial at ee201c wiki

3
Wire-bond vs Flip-chip
  • Wire bonding
  • Cheap Implementation
  • Difficult to design
  • IO signals are at boundary
  • High inductance (1nH)
  • More worry on core and IO power distribution
    during design and analysis

4
Wire-bond vs Flip-chip
  • Flip-chip
  • IO cells can be over entire of chip area
  • Low inductance (0.1nH)
  • High pin count, high cost
  • Less worry on power delivery

5
Silicon
Package
Board
(Cadence)
6
Connection from die to board
  • Die (IO cells -gt RTL routing -gt bumps)
  • -gt package (bumps -gt escape routing -gt package
    routing -gt balls)
  • -gt board

7
VLSI-Centric Design (Problematic)
  • IC and package tools very separated

(From P. Franzon)
8
On-Chip Design Concerns
  • Physical Concerns
  • Die Netlist Connectivity (logic cells to IO
    cells)
  • System Connectivity (IO cells to package)
  • Power Network (power planes to power IO cells to
    logic cells)
  • Electrical Concerns
  • Core Timing Constraints
  • System Timing Constraints
  • Power Budget
  • Signal Integrity and Reliability Constraints
  • Supply voltage scaling imposes very tight noise
    margins on chip and package designs
  • Significant noise contribution from core
    switching
  • But greater on-chip exposure to package-side
    (i.e., IO) SSN

9
Package Design Concerns
  • Physical Concerns
  • Reduce stack-up layers and package cost
  • Place IO cells and decoupling capacitance
  • Complete escaping and package routing
  • Electrical Concerns
  • Reduce SSN noise
  • Lower impedance of power distribution
  • Meet timing constraints, especially for bus and
    differential pairs

10
Typical Package Design Cycle
Pad/package Iteration PR of IO/Pad cells, Pins
Pwr/gnd and inter-cell connections PCB pin
locations (x,y)
Package/Pad/IO Rule checking (PRC) SI, timing,
clocks, IO voltages, assembly rules, special
regions
Floorplanning of IO/Pad/Pins Define Netlist
hierarchy/manipulations
Manufacturing and NRE Costs Die, Substrate,
Package
Verify user specified requirements and rules PCB
pins, Power grid, VSS/VDD, decoupling caps,
EMI, ESD, Vias
Defining Interfaces, Signals, PLL, Power, Clock,
pins, IOs
Package/Substrate Architecture Exploration
(start 4/5 months before Tapeout)
Finalize IOs/Pads/Pins Package Tapeout
11
Needs of Chip-Package Co-Design
  • High system frequency
  • 400 MHz buses becoming common
  • On-chip exposure to package noise
  • Simultaneous switching noise
  • Package resonance
  • High density packaging and high pin count
  • Difficult to layout and escape-route
  • Again, more SSN for on-die circuit
  • Tight time to market
  • Convergence of package and IO becomes a
    bottleneck if chip and package handled by
    separated flows

12
Keys Problems to Solve
  • Chip and package co-extraction and co-simulation
  • Difficult to obtain accuracy for sign-off
  • More difficult to achieve efficiency with
    accuracy or fidelity for planning and design
  • Challenging to handle mutual inductance and large
    number of ports
  • Co-design focuses on important links between chip
    and package
  • Chip side IO buffer design, noise isolation
    circuitry, P/G network, IO pad macro-placement,
    RDL estimation,
  • Package side Package stack-up, P/G plane design,
    macro-placement of balls and pins, and estimation
    of escape routing
  • key issues
  • IO planning and placement, power delivery system

13
Outline
  • Overview of Chip Package Co-design
  • IO planning and placement
  • Design constraints
  • Multi-stage solutions
  • Power integrity in package

14
Design Constraints for IO Planning and Placement
  • Power integrity
  • Timing
  • I/O standards
  • Core and board floorplanning

15
Power Integrity Constraints
  • Power domain constraint
  • I/O cell voltage specification
  • Cells from same domain prefer physically closer
  • Minimize power plane cut lines in the package
  • Provide proper power reference plane for traces
  • Depend on physical locations of I/O cells
  • Proper signal-power-ground (SPG) ratio
  • Primary and secondary P/G driver cells
  • Minimize voltage drop and Ldi/dt noise

16
Timing Constraints
  • Substrate routes in package varies significantly
  • Length spans from 1mm to 21mm
  • Timing varies more than 70ps for SSTL_2
  • I/O cells with critical timing constraints shall
    take this into account
  • Differential pairs and bus prefer to escape in
    parallel and in same layer

17
I/O Standard Related Constraints
  • High-speed design ? high-speed I/O
  • I/O standard requirements
  • Relative timing requirements on signals
  • Likely to be connected to the same interface at
    other chips, so prefer to keep relative order to
    ease routing
  • Closeness constraint
  • Less process variation
  • Bump assignment feasibility constraint

18
Floorplan Induced Region Constraints
  • Top-down design flow
  • PCB floorplan
  • Bottom-up design
  • Chip floorplan
  • I/O cells have region preference
  • Which side?
  • What location?

19
Connection from die to board
  • Die (IO cells -gt RTL routing -gt bumps)
  • -gt package (bumps -gt escape routing -gt package
    routing -gt balls)
  • -gt board

20
Flow of IO planning and placement
  • Global I/O and Core co-placement
  • Bump array Placement
  • I/O site definition
  • Constraint driven detailed I/O placement

21
Global I/O and Core Co-placement
  • Minimize both wire length and power domain
    slicing
  • Power domain plans I/O cells location, and
    becomes region constraints for I/O cells for the
    following steps

22
Bump and Site Definition
  • Regular bump pattern is preferred
  • Escapability analysis
  • Regular I/O site is preferred
  • I/O proximity
  • RDL planar routability analysis
  • I/O sites more than I/O cells
  • SPG ratio consideration
  • Flexibility for later bump assignment
  • I/O super site a cluster of I/O sites

23
Assign I/O Cells to Super I/O Sites
  • A set of region constraints (Ri, CiR)
  • A rectangular restricted area Ri for I/O cells
    CiR
  • E.g., floorplan, power domain definition, wire
    length minimization
  • A set of clustering constraints (Li, CiL)
  • The spread of I/O cells should be less than a
    bound
  • E.g., I/O standard const., floorplan, timing
  • A set of differential pair constraints
  • Different pairs should be connected to bumps with
    similar characteristics
  • E.g., timing
  • Solve by ILP or LP followed by netflow-based
    legalization
  • Paper 2C-4, Wednesday afternoon at this conference

24
Experiment Setting
  • Real industrial designs
  • Constraints not include the ones that are
    generated internally

25
Experiment Result
  • Obtain 100 CSR (constraint satisfaction ratio)
    in short runtime

26
Power Plane Cuts
Core Domain
Plane Cut
Island
IO Domain
27
Power Domain Routing
Domain Routing
28
Outline
  • Chip Package Co-design Flow
  • IO planning and placement
  • Power integrity in package
  • Overview and modeling
  • Decap insertion
  • Impedance based
  • Noise-based

29
Power Integrity
  • Time domain power and signal integrity
  • Signal Noise Analysis coupled with power plane
    models
  • Superposition of Power Noise on Signal Noise
  • IBIS, SPICE and PEEC models are employed
  • Frequency domain analysis of Power Planes
    Impedance
  • Return Path Modelling for EMI and SSN analysis
  • EMI Analysis
  • Package Plane Resonance

30
PDS Power Distribution System

Detailed Network Modeling is needed for accurate
analysis of Core and IO Power
31
Ideal Package Power Planes
  • Early Package Design Exploration
  • Planes have no holes or perforations
  • Perfect Microstrip or Stripline Patterns
  • Impedance is well conditioned

32
Non-ideal Package Power Planes
  • Detailed Plane Modeling
  • Planes are split for different voltage domains
  • Planes could have any number of holes /
    perforations
  • Microstrip or Stripline Patterns imperfect

33
PDS Modelling
  • Wire capacitance can be extraction using 2.5D
    model He-et al, DAC97
  • With extension to arbitrary routing angle
  • Plane capacitance needs to consider impact of
    wires in between
  • Inductance is must and can be formula based
  • Bonding wires have well controlled shapes
  • Susceptance (L-1) makes sparsification easier
  • But sign-off often needs 3D field solver

34
PDS Design
  • Assign power planes in package stackup
  • Assign power domains V18, V25, Vanalog,
  • Decide via stapling
  • Improve power delivery
  • Reduce current loop and eliminate noise
  • Assign P/G balls

35
PDS Concerns
  • DC Concerns
  • On-Chip IR Drop
  • Not a big concern in Flip-chip Designs
  • In-Package IR Drop
  • Important but still very small
  • In-PCB IR Drop
  • Can be ignored
  • AC Concerns
  • Low impedance Network across a broad frequency
    spectrum
  • Reduce inductive effective to reduce SSN
  • Control Chip/Package resonance

36
Power Plane Noise (AC vs DC)
37
PDS Design
  • PDS Impedance
  • Smaller Zo ? larger current
  • PDS Bandwidth
  • Maintain Zo from 0 to fmax
  • Decide on Decap Allocation
  • High speed drivers draw current from nearby
    decoupling capacitors
  • Decoupling capacitors reduce the size of the
    current loop

38
Chip-Package Plane Resonance
Resonances are produced due to inductance and
capacitance
Z
Capacitor becomes inductive beyond its self
resonant frequency, f(SR)
Inductive
Capacitive
frequency
Resonant frequency is
Need a set of capacitors to cover small, medium,
and high frequency ranges
39
Decoupling capacitors optimization
  • Needs for power integrity
  • Reduce resonance.
  • Reduce effective inductance and resistance.
  • Different levels of decoupling capacitors
  • Board, package, chip
  • Different effective frequency range.
  • Decoupling capacitors is not perfect capacitor
  • ESL
  • ESR
  • Lower ESL and ESR, higher cost
  • Designing of decoupling capacitors needs to
    determine
  • Values
  • Location
  • Decoupling capacitor type

40
Impact of decoupling capacitors
41
Existing Solutions
  • Manual trial-and-error approaches
  • Chen et al., ECTC 96
  • Yang et al., EPEP 2002
  • Automatic optimization
  • Kamo et al., EPEP 2000, Hattori et al., EPEP
    2002
  • Ignore ESL and ESR.
  • Zheng et al., CICC 2003
  • Use impedance as noise metric
  • Chen et al., ISPD 2006
  • Noise driven decap insertion

42
Limit of Impedance Metric
  • Can not capture noise accurately
  • Will Lead to large over-design

43
Incremental impedance computation
  • When adding one decoupling capacitor Zd at port k
  • the new impedance from port j to port i is
  • When removing one decoupling capacitor Zd at port
    k
  • the new impedance from port j to port i is

44
Time complexity
  • With one or a few decoupling capacitors inserted
  • O(np2) np is the number of ports
  • Existing work O(np3)
  • Especially suitable for trial-and-error or
    iterative methods
  • Only a few decoupling capacitors changed in each
    iteration
  • Able to compute only impedance or I/O ports
    before updating rest ports

45
Noise Calculation
  • FFT methods
  • Frequency components of noise from port j to port
    i
  • Worst case noise from all ports
  • Superposition

46
Algorithm
  • Simulated annealing with objective function
  • pi Penalty function for noise violation
  • ci cost of decoupling capacitor
  • a, ß weights

47
Example
  • 4 types of decoupling capacitors
  • 3 I/O ports
  • Each connected to 10 I/O cells
  • 90 possible location for decoupling capacitors
  • Total 93 ports
  • Worst case noise bound 0.35V

Power planes
Type 1 2 3 4
ESC(nF) 50 100 50 100
ESR(O) 0.06 0.06 0.03 0.03
ESL(pH) 100 100 40 40
Price 1 2 2 4
48
Experiment results noise based
Type 1 2 3 4
ESC(nF) 50 100 50 100
ESR(O) 0.06 0.06 0.03 0.03
ESL(pH) 100 100 40 40
Price 1 2 2 4
port 1 2 3
before optimization 2.52V 2.49V 2.48V
after optimization 0.344V 0.343V 0.344V
  • Cost20

49
Comparison Impedance Based
  • Cost72
  • 3X larger than noise based
  • Impedance bound is not met but noise bound has
    already been met.
  • Overdesign

port 1 2 3 bound
Maximum Impedance 5.31O 5.59O 7.12O 0.7O
worst-case noise 0.256V 0.302V 0.284V 0.35V
50
Runtime Comparison
1 Noise via incremental impedance decap
2 Noise via admittance matrix inversion Zhao et al, EPEP 2004 decap
3 Impedance decap Zheng et al, CICC 2003
approach 1 2 3
ports 93 93 20
iterations 5881 5403 1920
runtime(s) 389.5 4156.1 2916
avg. runtime(s) 0.0662 0.7692 1.519
  • 10x speedup compared to method based on
    admittance matrix inversion

51
Conclusions
  • High-speed IO signaling requires package-aware
    design and analysis (co-design)
  • Package-aware chip IO planning improves
    convergence and turnaround time
  • On-chip devices are increasingly exposed to
    package effects
  • Power integrity is getting harder
  • Efficient and accurate macro models are needed to
    enable chip-package co-design

52
24 reduction
Benefit of Chip-Package Co-Design (Design from
client of Rio Design Automation)
  • Package Size 27mm x 27mm
  • Substrate Layers 3-2-3
  • Original Die Size 7.2 x 7.4mm
  • New Die Size 6.3 x 6.5 mm
  • Voltage Domains 7
  • Two different voltages 3.3V, 1.8V
  • Total IOs 341
  • Frequency 200Mhz
  • Original Bump pitch x225, y225
  • New Bump Pitch X201, 225, 275
  • Y 216, 225
  • TSMC 0.18u process

53
Reading Assignment
  • J. Xiong, Y. Wong, E. Sarto, L. He, "Constraint
    Driven I/O Planning and Placement for
    Chip-package Co-design", IEEE/ACM Asia South
    Pacific Design Automation Conference, Jan. 2006.
  • J. Chen and L. He, Noise driven in-package
    decoupling capacitor optimization for power
    integrity," in International Symposium on
    Physical Design, 2006.

54
References
  • Extraction and sparsification
  • K. Nabors and J. White, "Fastcap A multipole
    accelerated 3-d capacitance extraction program,"
    IEEE Trans. on Computer-Aided Design of
    Integrated Circuits and Systems, pp. 1447-1459,
    Nov. 1991.
  • J. Cong, L. He, A. B. Kahng, D. Noice, N. Shirali
    and S. H.-C. Yen, "Analysis and Justification of
    a Simple, Practical 2 1/2-D Capacitance
    Extraction Methodology", ACM/IEEE Design
    Automation Conference, June 1997, pp.627-632.
  • M. Kamon, M. Tsuk, and J. White, "Fasthenry a
    multipole-accelerated 3D inductance extraction
    program," IEEE Trans. on MIT, 1994.
  • L. He, N. Chang, S. Lin, and O. S. Nakagawa, "An
    Efficient Inductance Modeling for On-chip
    Interconnects", IEEE Custom Integrated Circuits
    Conference, pp. 457-460, May 1999.
  • F. Grover, Inductance Calculations Working
    Formulas and Tables, Dover Publications, New
    York, 1946.
  • M. Beattie, H. Zheng, B. Krauter, A. Devgan,
    Spatially Distributed 3D Circuit Models,
    IEEE/ACM Design Automation Conference, 2005

55
References
  • Model order reduction
  • A. Odabasioglu, M. Celik, and L. Pileggi, PRIMA
    Passive reduced-order interconnect macro-modeling
    algorithm," IEEE Trans. on Computer-Aided Design
    of Integrated Circuits and Systems, pp. 645-654,
    1998.
  • R. W. Freund, SPRIM Structure-preserving
    reduced-order interconnect macro-modeling," in
    IEEE/ACM ICCAD, 2004.
  • H. Yu, L. He, and S. X.D. Tan, Block Structure
    Preserving Model Reduction, IEEE International
    Behavioral Modeling and Simulation Conference,
    September 22-23, 2005.

56
References
  • P/G noise
  • M. Zhao, R. V. Panda, S. S. Sapatnekar, and D.
    Blaauw, Hierarchical analysis of power
    distribution networks,'' IEEE Trans. on
    Computer-Aided Design of Integrated Circuits and
    Systems, no. 2, pp.159--168, 2002
  • E. Chiprout, Fast flip-chip power grid analysis
    via locality and grid shells,'' in ICCAD, 2004.
  • J. M. Wang and T. V. Nguyen, Extended Krylov
    subspace method for reduced order analysis of
    linear circuits with multiple sources," in Proc.
    Design Automation Conf. (DAC), 2000.
  • Y. Lee, Y. Cao, T. Chen, J. Wang, and C. Chen,
    HiPrime Hierarchical and passivity preserved
    interconnect macro-modeling engine for RLKC power
    delivery," IEEE Trans. on Computer-Aided Design
    of Integrated Circuits and Systems, vol. 26, no.
    6, pp. 797-806, 2005.
  • Y.Y Shi, H. Yu, and L. He, Generalized
    Second-Order Arnoldi Method for Model Order
    Reduction with Multiple Non-impulse Sources, ACM
    International Symposium of Physical Design, 2006.

57
References
  • IO planning and placement
  • W.-K. Mak, "I/O placement for FPGAs with multiple
    I/O standards," IEEE Trans. On Computer-Aided
    Design of Integrated Circuits and Systems, vol.
    23, pp. 315-320, February 2004.
  • J. Wang, K. Muchherla, and J. Kumar, "A
    clustering based area I/O planning for flip-chip
    technology," in Quality Electronic Design, 5th
    International Symposium on, pp.196-201, 2004.
  • A. Caldwell, A. Kahng, S. Mantik, and I. Markov,
    "Implications of area-array I/O for row-based
    placement methodology," in IC/Package Design
    Integration, IEEE Symposium on, pp. 93-98, Feb.
    1998.
  • M. M. Ozdal and M. D. Wong, "Simultaneous escape
    routing and layer assignment for dense PCBs," in
    Proc. Int. Conf. on Computer Aided Design, Nov.
    2004.
  • C. Tan, D. Bouldin, and P. Dehkordi, "Design
    implementation of intrinsic area array ICs," in
    Advanced Research in VLSI, Seventeenth Conference
    on, pp. 82-93, Sept. 1997.
  • J. Xiong, Y. Wong, E. Sarto, L. He, "Constraint
    Driven I/O Planning and Placement for
    Chip-package Co-design", IEEE/ACM Asia South
    Pacific Design Automation Conference, Jan. 2006.

58
References
  • Decoupling capacitors
  • L. Smith, R. Anderson, D. Forehand, T. Pelc, and
    T. Roy, "Power distribution system design
    methodology and capacitor selection for modern
    cmos technology," IEEE Transactions on Advanced
    Packaging, vol. 22, pp. 284-291, 1993.
  • H. Zheng, B. Krauter, and L. Pileggi, "On-package
    decoupling optimization with package
    macromodels," in Custom Integrated Circuits
    Conference, 2003.
  • J. Zhao and O. P. Mandhana, "A fast evaluation of
    power delivery system input impedance of printed
    circuit boards with decoupling capacitors," in
    IEEE Topical Meeting on Electrical Performance of
    Electronic Packaging, 2004.
  • J. Chen and L. He, Noise driven in-package
    decoupling capacitor optimization for power
    integrity," in International Symposium on
    Physical Design, 2006.
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