Reducing Clock Skew Variability via Cross Links

1
Reducing Clock Skew Variability via Cross Links

• LokWon Kim
• UCLA EE Ph.D. student
• Based on Anand Rajaram, Jiang Hu, and Rabi
  Mahapatra
• Dept. of Electrical Engineering
• Dept. of Computer Science
• Texas AM University

2
Presentation Outline

• Introduction
• Traditional approaches to skew variability
  reduction
• The proposed method
• Analysis on the method
• The optimized node selection algorithm
• Experimental results
• Conclusion

3
Clock Distribution Network
Register
Register

• Signal transfer coordinated by clock signal
• All registers are supplied with clock signal by
  clock distribution network
• Skew d1 d2
• Zero skew d1 d2
• Useful skew, d1 d2 d12

Dmax
1
2
d1
d2
Clock Network
4
Clock Tree Synthesis in Synchronous Circuits

• Clock signals synchronize data transfer between
  functional elements in synchronous design
• Clock skew becomes one of the most significant
  concerns in clock tree synthesis for high
  performance designs

5
Clock Distribution Networks Important
Considerations Objectives

• One of the biggest most frequently switching
  nets
• Very sensitive to unwanted skew introduced by
• Manufacturing variations
• Power supply noise
• Temperature variations
• Less skew variation is MUST for proper
  operation of chip
• Minimizing clock routing wire-length can
• Reduce power consumption
• Reduce power/ground noise

6
Sources of the Unwanted Skew Variations

• Process variations
• Gate variations
• Gate length variation
• Tox variation
• Interconnect variations
• Significantly affects delay and skew Liu, et
  al., DAC00
• Load capacitance variations
• Power supply noise
• Temperature variations

Gate variations
Interconnect width Variations
width
7
Non-tree Spine Kurd et.al JSSC01

• Applied in Intel Pentium processor design
• Variations between spines still exists

8
Non-tree Mesh

• Top level mesh Su et. al, ICCAD01
• Less wire, less effective

• Leaf level mesh Restle et. al, JSSC01
• Very effective, huge wire
• Applied in IBM microprocessor

9
The proposed method for reducing skew variability
10
Alternative View on Non-tree

• Non-tree tree links
• Link link_capacitors link_resistor

i
u
w
11
Mathematical analysis on the Link insertion method
12
The Elmore Delay in a RC network

• Cj is the ground capacitance at node j.
• Rij is equal to the voltage at node i when 1A
  current is injected into node j and all other
  node capacitors are zero.

Ri,w voltage at w
13
Effect of Link Capacitors on Delay

• Considering the effect of link capacitance only,
  the delay is

C Total link capacitance
i
C/2
C/2
14
Effect of Link Resistor on Delay Chan
Karplus, TCAD90
15
Skew Between Link Endpoints
16
Effect of Link Position
17
Skew Variability Between Any Nodes

• Skew variation between node i and node j
• Scenario1 i ? Tg , j ? Th variation smaller
• Scenario2 i j ?Tg(or Th) variation may be
  worse
• Scenario3 i ? Tp , j ? Tp variation may be
  worse

18
A Simple Example
The link pair number gives the rough order of
effectiveness in reducing skew variations
19
Optimized node selection algorithm based on the
analysis
20
General Flow of Non-tree Clock Routing

1. Obtain initial clock tree
2. Find node pairs for link insertion
3. Add link capacitances to selected nodes
4. Tune merging node location to restore original
   skew
5. Insert link resistance to selected node pairs

21
Guidelines for Node Pair Selection for Link
Insertion

• Select nodes which are hierarchically far apart
• Select nodes physically close to each other
• Select nodes with equal nominal delay
• Select nodes closer to leaf nodes

22
Rule Based Node Pair Selection
?-rule The nearest common ancestor's depth
from root is lt ?max
23
Experimental result to prove the proposed method
24
Experimental Result on Skew Variability
Benchmark r1 r2 r3 r4 r5
No. of sinks 267 598 862 1903 3100
25
HSPICE Validation
Benchmark r1 r2 r3 r4 r5
No. of sinks 267 598 862 1903 3100
26
Experimental Result on Wire-length
27
Cost vs. Benefit Analysis of Link Addition

• The Law of Diminished Returns holds!

28
Conclusions

• Effective link insertion methods has been
  proposed
• Significant skew variability reduction with
  limited wire-length increase
• Proposed methodology is independent of the nature
  of variability effects