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Kazi Fall 2007 EEGN 494

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Title: EENG 494 HDL Design Principles for VLSI/FPGA Author: Khurram Kazi Last modified by. Created Date: 8/24/2002 8:20:43 PM Document presentation format – PowerPoint PPT presentation

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Title: Kazi Fall 2007 EEGN 494


1
EEGN-494 HDL Design Principles for VLSI/FPGAs
  • Khurram Kazi

2
Course Outline
  • Overview of ASIC design flow
  • Behavioral modeling for Test Benches in VHDL
  • VHDL for Synthesis
  • Constraining and Optimizing Design
  • Self Checking Design Verification Concepts
  • Verilog for Synthesis
  • Gate Level Verification

3
Recommended Books useful links
  • Circuit Design with VHDL, Volnei A. Pedroni, MIT
    Press, 2004, ISBN 0-262-16224-5
  • Verilog HDL, Samir Palnitkar, 2nd Edition,
    SunSoft Press A Prentice Hall Title, 2003, ISBN
    0-13-044911-3
  • HDL Programming Fundamentals VHDL and Verilog,
    Nazeih, B. Botros, Da Vinci Engineering Press,
    2006, ISBN 1-58450-855-8
  • Advanced ASIC Chip Synthesis Using Synopsys
    Design Compiler and PrimeTime, Himanshu
    Bhatnagar, Kluwer Academic Publishers, 2nd
    Edition, ISBN 0-7923-7644-7
  • http//ece.gmu.edu/courses/ECE545/index.htm
  • This webpage has tons of useful information!!
  • Go over the ModelSim content as we will be using
    it as the simulator

4
Grading Policy
  • Homework/mini projects 40
  • 1 Midterm Test 20
  • Final Project 40
  • Homework and Final Projects can be customized to
    your field of specialization, may it be in Data
    Networking, Cryptography, Specialized Arithmetic
    Operations, DSP, Computer Architecture etc.
  • Oral and written communication skills will be
    stressed in this course and taken into account
    for the final grade

5
Dos and Donts for the Final Project
  • DO NOT use any off the shelf general purpose
    microprocessor or any other circuit taken from
    the publicly available information base.
  • Come up with your own functional idea and
    Implement it. Be creative! Have a systems
    perspective and see how your design fits in the
    system.

6
Teamwork Encouraged How much collaboration is
acceptable
  • Since time will be short, I would encourage you
    to help out your fellow students with the Usage
    of the Tools and not the Design. Informing me of
    the help received is strongly encouraged, i.e.
    give credit where credit is due!!
  • Helping fellow students with Tools usage and
    class participation will be rewarded in the final
    grade.

7
Where to Start in the ASIC Process!
  • Begin with ASIC Specification (most likely by the
    time you are done with the design the Final Spec.
    will be quite different than the original ideas)
  • Based on performance requirements define
    operating frequencies, I/O pad types, operating
    conditions, verification and test requirements to
    ensure error free design and manufacturability

8
Implication of the Designs we work on keep few
things in mind!
  • During the design process we always make
    trade-offs
  • Trade-offs can be based on time to market, cost
    implications, complexity, environmental
    considerations etc.
  • Ethics Keep in mind the implications of what you
    are designing, how it impacts the society!!
  • Digital designs inherently deal with
  • Implementing approximate solutions
  • Power consumption considerations Making the
    Designs Green Environmental friendly!!
  • Cost/performance trade-offs

9
Implication of the Designs we work on keep few
things in mind!
  • Few bad approximations lead to
  • Example Failure of Patriot Missile (1991 Feb.
    25)
  • Source http//www.math.psu.edu/dna/455.f96/disaste
    rs.html
  • American Patriot Missile battery in Dharan, Saudi
    Arabia, failed to intercept incoming Iraqi Scud
    missile The Scud struck an American Army
    barracks, killing 28
  • Cause, per GAO/IMTEC-92-26 report software
    problem (inaccurate calculation of the time
    since boot)
  • Specifics of the problem time in tenths of
    second as measured by the systems internal clock
    was multiplied by 1/10 to get the time in seconds
    Internal registers were 24 bits wide 1/10
    0.0001 1001 1001 1001 1001 100 (chopped to 24 b)
    Error _at_ 0.1100 1100 2 23 _at_ 9.5 10 8 Error
    in 100-hr operation period _at_ 9.5 10 8 100
    60 60 10 0.34 s
  • Distance traveled by Scud (0.34 s) (1676 m/s)
    _at_ 570 m, this put the Scud outside the Patriots
    range gate. Ironically, the fact that the bad
    time calculation had been improved in some (but
    not all) code parts contributed to the problem,
    since it meant that inaccuracies did not cancel
    out

10
Implication of the Designs we work on keep few
things in mind!
  • Few bad approximations lead to
  • Example Explosion of Ariane Rocket (1996 June 4)
  • Source http//www.math.psu.edu/dna/455.f96/disaste
    rs.html
  • Unmanned Ariane 5 rocket launched by the European
    Space Agency veered off its flight path, broke
    up, and exploded only 30 seconds after lift-off
    (altitude of 3700 m). The 500 million rocket
    (with cargo) was on its 1st voyage after a decade
    of development costing 7 billion
  • Cause software error in the inertial reference
    system
  • Specifics of the problem a 64 bit floating point
    number relating to the horizontal velocity of the
    rocket was being converted to a 16 bit signed
    integer
  • An SRI software exception arose during
    conversion because the 64-bit floating point
    number had a value greater than what could be
    represented by a 16-bit signed integer (max 32
    767)

11
Overview of Some of the steps in an ASIC design
flow
12
RTL Block Synthesis
Simplified design flow
13
Insert Test Structure (Internal Scan and JTAG)
Note that we will not cover JTAG or insertion of
the boundary scan in this class
Simplified design flow
14
Insert Test Structure (Internal Scan and JTAG)
Note that we will not cover JTAG or insertion of
the boundary scan in this class
Simplified design flow
15
Insert I/O Pads
Simplified design flow
16
ASIC Floorplan
Simplified design flow
17
Getting ASIC Ready for Handoff
Simplified design flow
18
Brief History of VHDL
  • VHDL is a language designing and simulating
    digital hardware. It has been adopted by the
    electronics industry worldwide. Another Language
    that is also widely used is Verilog
  • VHDL is an acronym for VHSIC (Very High Speed
    Integrated Circuit) Hardware Description Language
  • VHDL originally was used for specifications
  • Subsequently was used for simulating designs
  • Finally its scope evolved into its usage for
    synthesizing digital designs

19
Levels of Abstraction
Algorithmic level
Level of description most suitable for synthesis
Register Transfer Level
Logic (gate) level
Circuit (transistor) level
Physical (layout) level
Slide taken from K.Gaj lectures at GMU
20
Register Transfer Logic (RTL)
Registers
Slide taken from K.Gaj lectures at GMU
21
Levels at which VHDL can be used
  • VHDL for Specification

VHDL for Simulation
VHDL for Synthesis
Slide taken from K.Gaj lectures at GMU
22
Typical HDL Design Environment
HDL Design (VHDL or Verilog
Testbench (Analyzer In C or HDL)
Testbench (Generator In C or HDL)
Reference Model ( In C or Functional HDL)
23
Overview of VHDL
  • Library and Library Declarations
  • Entity Declaration
  • Architecture
  • Configuration

24
Overview of VHDL
  • Package (typically compiled into the destination
    library) contains commonly used declarations
  • Constants maybe defined here
  • Enumerated data types (Red, Green, Blue)
  • Combinatorial functions (performing a decode
    function returns single value)
  • Procedures (can return multiple values)
  • Component declarations

25
Overview of VHDL Example of Library Declaration
  • LIBRARY library_name --comments
  • USE library_name.package_name.package_parts --
    VHDL is case -- insesitive
  • Typically there are three different libraries
    used in a design
  • ieee.std_logic_1164 (from the ieee library)
  • standard (from the std library)
  • work (work library)
  • std_logic_1164 Specifies the STD_LOGIC (8
    levels) and the STD_ULOGIC (9 levels)
    multip-values logic systems
  • std It is a resource library (data types, text
    i/o, etc.)
  • work This is where the design is saved
  • Library ieee -- A semi-colon () indicates the
    end of a statement or a declaration
  • USE ieee.std_logic_1164.all -- double dash
    indicates a comment.
  • Library std
  • USE std.standard.all
  • Library work
  • USE work.all

26
Overview of VHDL Entity
  • Entity
  • Defines the component name, its inputs and
    outputs (I/Os) and related declarations.
  • Can use same Entity for different architecture to
    study various design trade offs.
  • Use std_logic and std_logic_vector(n downto 0)
    they are synthesis friendly.
  • Avoid enumerated type of I/Os.
  • Avoid using port type buffer or bidir (unless
    have to)

27
Overview of VHDL Syntax of an Entity
  • ENTITY entity_name IS
  • PORT (
  • port_name signal_mode signal type
  • port_name signal_mode signal type
  • .)
  • END entity_name
  • ENTITY nand_gate IS
  • PORT (
  • a IN std_logic
  • b IN std_logic
  • x OUT std_logic)
  • END nand_gate
  • or
  • ENTITY FiveInput_nand_gate IS
  • PORT (
  • a IN std_logic_vector (4 downto 0)
  • x OUT std_logic)
  • END FiveInput_nand_gate

28
Overview of VHDL Architecture
  • Architecture
  • Defines the functionality of the design
  • Normally consists of processes and concurrent
    signal assignments
  • Synchronous and/or combinatorial logic can be
    inferred from the way functionality is defined in
    the Processes.
  • Avoid nested loops
  • Avoid generate statements with large indices
  • Always think hardware when developing code!
  • One way of looking at is how would you implement
    the digital design on the breadboard, mimic the
    same thought process in writing VHDL code

29
Overview of VHDL Syntax of an Architecture
  • ARCHITECTURE architecture_name OF entity_name IS
  • declarations
  • BEGIN
  • (code)
  • END architecture_name
  • ARCHITECTURE myarch OF nand_gate IS
  • BEGIN
  • x lt a NAND b
  • END myarch

30
Overview of VHDL Basic Components of an
Architecture
  • Primarily Architecture consists of
  • Process
  • Concurrent Statements
  • Code in VHDL is inherently concurrent (parallel)
  • All processes and concurrent statements are
    evaluated in parallel (i.e. at the same time)
  • Code inside the process is executed sequentially
  • The code execution is based on sensitivity list
    (signals that act as triggers in the execution of
    the respective process
  • Process can describe
  • Asynchronous (combinatorial logic)
  • Synchronous (clocked logic)
  • Concurrent Statements
  • Typically combinatorial logic is implemented
    using concurrent statements

31
Separation of Combinatorial and Sequential Logic
Signals within the sensitivity list
32
Case statement Synthesis
33
Synthesis of if then elsif statement
34
Overview of VHDL
  • Configuration
  • Primarily used during the simulations
  • If there are multiple architectures for the same
    entity, the configuration can be used to
    instruct the simulator which architecture should
    be used during the simulation.

35
Some useful practices
  • Organize Your Design Workspace
  • Define naming convention (especially if multiple
    designers are on the project
  • Completely Specify Sensitivity Lists
  • Try to separate combinatorial logic from
    sequential logic

36
Assignment 1
  • Define the entity of a 16 bit up-down counter
  • It should have a clock, up-down control bit,
    reset (active low, i.e. the counter should be in
    a reset state when reset pin is asserted low)
  • How many output ports will the counter have?
  • Define an entity of an 8 bit shift register that
    shifts data from left to right.
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