Lecture 15 PicoBlaze I/O

1
Lecture 15PicoBlaze I/O Interrupt Interface
ECE 448 FPGA and ASIC Design with VHDL
2
Required reading

• P. Chu, FPGA Prototyping by VHDL Examples
• Chapter 16, PicoBlaze I/O Interface
• Chapter 17, PicoBlaze Interrupt Interface

3
Syntax and Terminology
Syntax Example Definition
sX KK PORT(KK) PORT((sX)) RAM(KK)
s7 ab PORT(2) PORT((s1)) RAM(4)
Value at register 7 Value ab (in hex) Input value
from port 2 Input value from the port specified
by register s1 Value from the RAM location 4
4
Addressing modes
5
Output Decoding of Four Output Registers
6
Output Instructions
C Z
OUTPUT sX, KK PORT(KK) lt sX OUTPUT
sX, (sY) PORT((sY)) lt sX
- -
DIR IND
- -
7
Timing Diagram of an Output Instruction
8
Truth Table of a Decoding Circuit
9
Input Instructions
C Z
INPUT sX, KK sX lt PORT(KK) INPUT sX,
(sY) sX lt PORT((sY))
- -
DIR IND
- -
10
Block Diagram of Four Continuous-Access Ports
11
Timing Diagram of an Input Instruction
12
Block Diagram of Four Single-Access Ports
13
FIFO Interface
clk
rst
clk
rst
FIFO
dout
din
8
8
empty
full
write
read
14
Operation of the Standard FIFO
A
B
C
D
-----
15
Operation of the First-Word Fall-Through FIFO
16
(No Transcript)
17
Timing Diagram of an Input Instruction
18
Interrupt Flow
19
Timing Diagram of an Interrupt Event
20
(No Transcript)
21
Interrupt Related Instructions
RETURNI ENABLE PC lt STACKTOS TOS
lt TOS 1 I lt 1 Clt PRESERVED C
Zlt PRESERVED Z RETURNI DISABLE PC
lt STACKTOS TOS lt TOS 1 I lt 0
Clt PRESERVED C Zlt PRESERVED Z ENABLE
INTERRUPT I lt1 DISABLE INTERRUPT
I lt0
22
Interrupt Interface with a Single Event
23
Interrupt Interface with Two Requests