EE- 584

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EE- 584 DESIGN
AND TESTING OF A CMOS INVERTER
LAKSHMAN KUMAR GOKAVARAPU
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OBJECTIVE Design and test the working of an
inverter using Mentor graphics Software.
STEPS ADOPTED 1) Design of schematic using
Design Architect
2) Testing the functionality of schematic
using
quicksim. 3)
Design of Layout corresponding to schematic using
IC
workstation.
4) Verification of Layout using DRC rules LVS
report. 5)
Parameter extraction using IC extract.
6) Testing the
functional correctness of Layout using
accusim.


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TRUTH TABLE
IN OUT
1 0
0 1
Schematic of inverter
Fig.1
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Symbol of inverter
Fig.2
Quicksim Simulation Results
Fig.3
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Layout
Fig.4
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DRC rules Define the spacing between various
layers , which should be followed during
designing a layout. The following are some of the
rules 1) 2?-Minimum width of
poly. 2) 2?-Minimum width and length
of contact. 3) 2?-Minimum extension
of poly beyond diff. 4) 1.5?-Minimum
enclosure of contact by diff. 5)
2?-Minimum spacing between contact and poly.
6) 3?-Minimum poly-poly interspacing.
LVS Report The layout versus schematic tool
(LVS) checks whether the
layout matches with the schematic in terms of
number of ports and
instances.
7
Fig.5
PARAMETER EXTRACTION Done to extract and back
annotate the lumped
parameters. The value of
the lumped parameters
including intrinsic
capacitances could be obtained.
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Accusim Results
Fig.6
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ConclusionsCMOS inverter was designed using
Mentor Graphics tool. The
layout was designed with minimum total area and
the inverter was verified
for its functionality.