Interconnect%20Dominated%20Design%20and%20Analysis

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Interconnect Dominated Design and Analysis
Chung-Kuan Cheng
CSE Department UC San Diego ckcheng_at_ucsd.edu
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Research Scope

• Packaging architecture
• Replace current backplane, board, substrates
• SPICE_Diego Thermal, Mechanical Simulation
• Heart Beat Aids

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Research Results

• Architecture Designs, Hardware Systems, Software
  Packages
• Quality of Patents
• Technical Books
• Journal Papers, Conference Papers

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Research Process

• Why
• What
• Where
• How

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Research Subjects

• Scalable System Power, Delay, Cost, Reliability
• A Analysis Spice, Power, Clock, Variations (STA)
• B BioEng EKG, Signal Network
• C Interconnect Networks Packaging, Interconnect,
  Networks
• D Data path Adders, Shifters, CMDL

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A Analysis

• Spice Parallel Computing, Operator Splitting
• Power
• Analysis in t and s domains, Natural Frequency
  (GjwC)-1
• Synthesis of networks and decap.
• Clock
• Analysis and synthesis of mesh and tree
• Variations Stochastic Process, Monte Carlo
• Altera, Fastrack, Fujitsu, Qualcomm, Synopsys
• Rui, Vincent, Ling, Wanping, Renshen

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B BioEng

• EKG Probe, Measurement, Algorithm
• Signal Networks
• Yi, Wanping

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C Interconnect Networks

• Packaging
• 3D Floorplanning, Pin Breakaway, Signal Integrity
• Interconnect
• Passive Wire Technologies
• Networks
• Hierarchy, Topology, Performance
• ADS, HFSS, EIP, PowerSpice, Sigrity
• Yuanfang, Haikun, Yi, Renshen

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D Data Paths

• Shifters
• Adders Lings adder, High Radix
• Differential Circuit Style
• Haikun, Yi, Ling, Renshen

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Process

• Research as the highest priority (Call me
  anytime)
• Follow-up and go through the exploration (Dont
  drop the ball)
• Plan ahead (Schedule, Proactive)
• Utilize the team (Establish Personal Networks)

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Group Presentation

• Statement of the problem
• Previous Schedule
• Progress Report
• Weekly and Monthly Schedule

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Presentations

• Main theme of the talk
• Key point of each page
• Practice
• Audio tape recording
• Questions and Answers
• Problems behind the questions