Combinatorial Circuits III - PowerPoint PPT Presentation

1 / 12
About This Presentation
Title:

Combinatorial Circuits III

Description:

Combinatorial Circuits III The Half Adder, the Full Adder, the DeMux, the Encoder How do you add 2 bits? A B|S C 0 0|0 0 S = 0 1|1 0 1 0|1 0 C = 1 1|0 1 ... – PowerPoint PPT presentation

Number of Views:96
Avg rating:3.0/5.0
Slides: 13
Provided by: Nauze
Category:

less

Transcript and Presenter's Notes

Title: Combinatorial Circuits III


1
Combinatorial Circuits III
  • The Half Adder, the Full Adder,
  • the DeMux, the Encoder

2
How do you add 2 bits?
  • A BS C
  • 0 00 0 S
  • 0 11 0
  • 1 01 0 C
  • 1 10 1
  • Why Half?

S
A
H.A
B
C
3
The Half Adder
4
The Full Adder
  • Truth table
  • Sum
  • C_out

A
S
HA
HA
Cin A B S C_out
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
C
B
5
Full Adder
6
The n-bit Ripple Carry Adder
a an-1.a2a1a0 b bn-1.b2b1b0
an-1
bn-1
a2
b2
a0
b0
a1
b1
c0
c1
FA
FA
FA
FA
??
.
cout ?
sn-1
s2
s1
s0
7
RippleCarry Adders (contd.)
  • Ripple-carry adders can be slow
  • Delay proportional to number of bits added
  • Carry lookahead adders
  • Eliminate the delay of ripple-carry adders -
  • Impl. carry in 2 parts Gi Ai.Bi Pi Ai xor
    Bi
  • then Ci1 Gi Pi.Ci etc.
  • Carry-ins are generated independently
  • C0 A0 B0
  • C1 A0 B0 A1 A0 B0 B1 A1 B1
  • . . .
  • Requires complex circuits
  • Usually, a combination carry lookahead and
    ripple-carry techniques are used

8
Practical Devices Programmable Logic Arrays
  • PLAs (also fPGA field P Gate A)
  • Implement sum-of-product expressions
  • No need to simplify the logical expressions
  • Take N inputs and produce M outputs
  • Each input represents a logical variable
  • Each output represents a logical function output
  • Internally uses
  • An AND array
  • Each AND gate receives 2N inputs
  • N inputs and their complements
  • An OR array

9
A 2 i/p 2 o/p PLA
10
Implementation of Boolean Functions using PLAs
11
The Demux
  • The inverse of the MUX it has
  • 2n outputs, 1 input and n selectors
    (addressing) terminals
  • a2 a1 a0 d x7 x6 x5 x4 x3 x2 x1 x0
  • -------------------------------------
  • 0 0 0 c 0 0 0 0 0 0 0 c
  • 0 0 1 c 0 0 0 0 0 0 c 0
  • 0 1 0 c 0 0 0 0 0 c 0 0
  • 0 1 1 c 0 0 0 0 c 0 0 0
  • 1 0 0 c 0 0 0 c 0 0 0 0
  • 1 0 1 c 0 0 c 0 0 0 0 0
  • 1 1 0 c 0 c 0 0 0 0 0 0
  • 1 1 1 c c 0 0 0 0 0 0 0
  • Used to send data from a single source to one of
    a number of destinations. Is also a universal
    gate
  • (assign 2).

12
Encoder/ Priority encoder
Table for a priority encoder
  • A 2n to n device that delivers the binary index
    of a bit pattern.
  • Trouble with straight encoder.
  • Hence
  • The MSB has highest priority etc.
  • Used when multiple devices use the same resource.
    Each device is granted a priority that is used to
    resolve any conflicts.
  • (circuit in class)
Write a Comment
User Comments (0)
About PowerShow.com