Cambridge University

1
EUDET/CALICE DAQ Overview

• Cambridge University
• Imperial College London
• University of Manchester
• Royal Holloway, University of London
• University College London
• Matthew Warren, UCL
• 22 March 2007

2
Ideal DAQ Structural Overview
ASICs
ASICs
ASICs

• Detector ASICs on e.g. ECAL slab
• Front-End (FE)
• FE-Interface (DIF) Detector specific
• FE Link/Data Aggregator (LDA) Generic
• Data-link (FE to Off-Detector Receiver)
• CCC-link (ClockControlConfig to FE)
• DAQ PC
• Off-Detector Receiver/s (ODR)
• Drives CCC-link
• Data Store

DIF
DIF
DIF
FE
LDA
Data-link
CCC-link
PC/s
ODR
Store
3
FE Structure Detail

• We have 2 types of detector to readout.
• Divide the FE into a 2 part, tiered system
• 1) Detector Interface module (DIF)
• Detector specific interface
• Includes power connectors
• Local systems (e.g. stand-alone clock)
• Debug connectors
• 2) Link/Data Aggregator module
• (LDA)
• Collects data from many DIFs
• Drives data Off detector link
• Receives and distributes CC
• FPGA Development board
• BUT
• We would might like to read-out slabs
  individually first

ECAL Slab
ECAL Slab
HCAL Layer
HCAL Layer
ECAL DIF
HCAL DIF
HCAL DIF
ECAL DIF
Link/ Data Aggregator
Link/ Data Aggregator
CC Fanout
PC
PC
4
Data-link (CCC)

• Use most common networking fibre-optics
• Multimode with LC connectors
• SFP (mini-GBIC) interfaces
• 1Gbit rate (maybe tuned to multiple of machine
  freq.)
• Ethernet
• Control up-link NOT via fibre, initially.

5
Off-Detector Receiver (ODR)

• PCI Express Card
• Virtex 4, FX100 FPGA (big!)
• Hosts opto-links
• 2xSFP, 2xHSSDC2 on board
• Source of CC (Control link)
• Initially copper (LVDS)
• Later fibre
• Will use external clock and sync signals for
  multi-board synchronous operation

6
ODR(2) - Status

• Firmware AND software well underway
• PCIe interface DONE
• Register read/write DONE
• DMA access DONE
• Ethernet Interface
• IN-PROGRESS
• DDR2 Interface IN-PROGRESS
• Linux driver DONE
• Optimised Disk Store
• IN-PROGRESS
• Manager Software
• IN-PROGRESS
• Performance profiling
• IN-PROGRESS
• Clock and Control Uplink
• NOT-STARTED

Ethernet Interface
DDR2 Interface
Internal RAM
Test Data Gen
Arbiter
Control/ Status Reg. Block
PCIe Interface
Firmware
Driver
Manager
Software
7
UK Read-out work (ECAL FE)
ECAL Slab

• Detector Interface (Cam, IC)
• Spec hardware
• DIF to Link/Data Aggregator (Cam/Man)
• Spec hardware
• Data aggregate, format (Man)
• Hardware firmware
• LDA to ODR opto-link (Man, UCL)
• Hardware firmware
• ODR (RHUL, UCL, Cam)
• firmware
• ODR to disk (RHUL)
• Driver software
• Local Software DAQ (RHUL)
• Full blown Software DAQ (RHUL, UCL, IC)

DIF
LDA
Opto
PC
ODR
Opto
Driver
8
Clock Control, Integration

• Keep it simple!
• -System synchronising signals distributed
• All data tagged with common timestamp

Clock Control (Train-start, Sync)
Slave out
Master In
Slab
LDA
Slab
PC
Slab
Fanout (TLU?)
ODR
Config
ODR
Slab
PC
LDA
Slab
ODR
Slab
Config
ODR
9
TLU Requirements

• Lets assume 32 Slabs.
• Each Slab needs Clk Train, (Trigger?)
• But could use LDA here. At 8 slabs/LDA 4 LDAs
• With minimum 1 LDA/ODR 4 ODRs
• Each ODR needs same Fast Control(data)
• 4 Signals Clock, Train, Trigger, Control
• Fanout of 32 slabs 4 LDA 4 ODE 40,
• OR more likely 4 LDA 4 ODR 8.
• TLU acts as Master or Slave for signalling
• TLU generates signals stand-alone
• We presume to use LVDS everywhere.
• ?? Do we try to use the TLU for fanout, or just
  as a machine interface?

10

• Extra
• Optical Switch

11
Optical (Layer-1) Switching

• Part of the UK CALICE is to evaluate the use of a
  layer-1 switch.
• 1) DAQ PC failover - Redirect data to spare
  unused DAQ PC on the fly
• 2) Router - Can change data destination per
  bunch-train.
• Regulate load by sending data directly to free
  resources
• 3) Programmable optical patch panel (large
  installation)
• Manufacturers offering similar products, in same
  price range e.g. Glimmerglass, Polatis -
  difficult to differentiate between them
• Decided on Polatis
• can switch dark fibre (i.e. not MEMS based)
• Multimode fibre capable
• Fastest switching time (20ms)
• 16x16 array with 50µm multimode LC connectors