HDL-Based Layout Synthesis Methodologies

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HDL-Based Layout Synthesis Methodologies

• Allen C.-H. Wu
• Department of Computer Science
• Tsing Hua University
• Hsinchu, Taiwan, R.O.C
• Email chunghaw_at_cs.nthu.edu.tw

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Outline

• Introduction
• Timing analysis
• Design planning
• RTL timing budgeting
• A timing-driven soft-macro placement and
  resynthesis method
• Discussion

3
Why Needs HDL-based Design Methodologies?
Design complexity
Then
Now
Schematic capture
HDL design specification
Component mapping may be some logic
optimization
Synthesis
Place route
Place route
Layouts
Layouts
SW assembly language gt high-level language
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An HDL-based Design Flow
HDL design specification
HDL coding styles
Applications
RTL synthesis
Logic synthesis
Cell libraries
Layout architectures
Layout synthesis
Layouts
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Top-Down Design Methodology
HDL design specification
Preserving design hierarchy
RTL synthesis
Bridging the gap between RTL, logic, and
layout synthesis
Logic synthesis
Layout synthesis
Layouts
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Applications and Layout Architectures

• Datapath dominated designs DSPs and processors.
• Control dominated designs controllers and
  communication chips.
• Mixed type of designs.

• Bit-sliced stacks.
• Standard cells.
• Macro-cell-based.
• FPGAs.

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Layout-driven Design methodology
HDL design specification
RTL synthesis
Multi-level estimation engine
Logic synthesis
Back annotation
Layout synthesis
Layouts
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Design Estimation

• Timing
• Area
• Power
• Statistic VS. quick-synthesis methods
• Analytical VS. constructive methods

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Outline

• Introduction
• gtTiming analysis
• Design planning
• RTL timing budgeting
• A timing-driven soft-macro placement and
  resynthesis method
• Summary

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Minimum Cycle Time
Critical path delay
Clock skew
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Timing Analysis

• Critical path delay analysis
• Clock skew analysis
• Timing analysis at different design levels
• Delay calculation
• Parasitic extraction
• Accuracy VS. fidelity

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Timing Analysis
HDL design spec.
HDL specification
RTL synthesis
Logic equations
Logic synthesis
Accuracy
Complexity
Cell-based netlists (Tech. dependent or
independent)
Layout synthesis
Floorplanning and P R
Layouts
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RTL and Logic-level Timing Analysis
HDL Spec.
Macro
Macro
Macro based
Logic equations
Outputs
Inputs
Macro
Cell-based netlist
Unit and zero delay models for cells and wires
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RTL Timing Analysis
HDL design spec.
A
Aspect ratio
A
Aspect ratio
Macro
Macro
T
T
Floorplanning
Re-synthesis re-floorplanning
Back annotation
3
3
1
1
4
4
2
2
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Chip-level Timing Analysis
Macro cells

• Taken into account inter-macro wiring delays.
• Chip-level path enumeration.
• Estimation vs. back annotation.

Floorplanning
Layout extraction
Wiring delay
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Macro-level Timing Analysis
Netlists

• Taken into account intra-macro wiring delays.
• Path delay enumeration.
• Estimation vs. back annotation.

P R
Layout extraction
Wiring delay information
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Accuracy of Timing Analysis
Design Stages
Accuracy
RTL
100/-50???
Floorplanning
100/-25
Placement
100/-15
Global routing
100/-7
Detailed routing
100/-0
Source DAC97 Tutorial by Blaauw_Cong_Tsay
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Outline

• Introduction
• Timing analysis
• gt Design planning
• RTL timing budgeting
• A timing-driven soft-macro placement and
  resynthesis method
• Summary

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Design Planning

• Macro definitions
• Soft macro generation
• Macro placement
• Pin assignment

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Chip Planning I
Soft macros
Hard macros
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Chip Planning II
Soft macros
Hard macros
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Design Planning Considerations

• How much timing, area, and power budgets should
  be assigned to each macro?
• How to generate soft macros?
  - top-down
  - bottom-up
  
• How to layout clock and power/ground network?

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Design Budgeting
Driving resistance
Load capacitance
Macro
Arrival time
Required arrival time
RTL Spec.
RTL Logic synthesis
Netlists
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Soft Macro Generation
Partitioning
SM
SM
SM
Clustering
Based on design hierarchical information
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Soft Macro Generation (Cont.)
Perform clustering techniques on a flattened
netlist
Clustering criteria . Timing . Interconnect
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Design Hierarchy Preservation
HDLs
Verilog design spec.
Mod1
Mod2
Mod3
HDL synthesis
Macro formation
Macro placement
Macro to cell placement
Initial placement
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Clock Network Styles

• Mesh robust, large area and power
• Trunk simple
• Tree min area, many supporting design algorithms

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Clock Issues at RTL
Critical path is determined from clock skew
and skew cannot be determined until placement
is completed!
How to incorporate clock skew issues into
early design planning???? Still an open problem!
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RTL Timing Analysis
HDL design spec.
A
Aspect ratio
A
Aspect ratio
Macro
Macro
T
T
Floorplanning
Re-synthesis re-floorplanning
Back annotation
3
3
1
1
4
4
2
2
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Timing-critical Macro Detection
HDL Spec.
HDL spec.
Macro
Macro
HDL synthesis
Critical macro
Floorplanning
Chip-level timing analysis
Back annotation
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RTL Design Planning
Floorplanning
HDL Spec.
Macro
Macro
Back-annotation
Delay area estimations
Cell library
RTL timing analysis
Constructive or analytical method
Back-annotation
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Outline

• Introduction
• Timing analysis
• Design planning
• gt RTL timing budgeting
• A timing-driven soft-macro placement and
  resynthesis method
• Summary

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RTL Design Budgeting
Loop
Area Delay Power
Budget?
Loop
Loop
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Timing Budgeting
Cross-macro timing paths!!!
1 Cycle
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Timing Budgeting Issues

• How to estimate delay and area from RTL
  specification???
• After floorplanning? After RTL/logic synthesis?
  After placement? After routing?
• Run time VS. accuracy?
• How to distribute timing budget among macros?
• No much work has been done in this area!!!

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Timing Budgeting for Design Optimization
Minimize total area subject to satisfying the
timing constraints.
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Outline

• Introduction
• Timing analysis
• Design planning
• RTL timing budgeting
• gt A timing-driven soft-macro placement and
  resynthesis method
• Summary

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A Typical Design Flow for Macro-based Design
Back-annotation
HDL Synthesis
Timing Analysis
No
OK?
Floorplanning
Yes
P R
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Design Hierarchy Preservation
Preserving HDL design hierarchy for
soft-macro placement?
HDL Description
HM
M1
HM
M_11
M2
SM
M_12
HM
A complete chip design methodology?
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Considerations

• How to utilize HDL design-hierarchy information
  to guide soft-macro placement procedure?
• How to integrate design tasks and point tools at
  different design level to form a complete chip
  design methodology?
• How to exploit the interaction between different
  design tasks.

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Design Flow for Design Hierarchy Preservation
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Structural-tree Construction

• The main objective is to preserve the design
  structural information from an HDL design
  description for macro formation.

Top
SM4,5
SM1,2
HM1
HM2
SM1
SM2
SM3
SM4
SM5
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Soft macro Formation

• Decomposition of large soft macros.
  - A large macro is too rigid for macro placement.
• Clustering of small soft macros.
  - Many small macros increase the computational
  complexity.

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Soft Macro Placement

• Inputs a set of software macros and the
  available area for soft macros.
• Outputs the relative location of each soft macro
  on the layout plane.
• 1st step force-directed-based placement.
• 2nd step Sweeping-based soft-macro assignment.

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Floorplanning and Soft-Macro Area Extraction
HM
HM
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Force-directed-based Placement
HM
SM4
HM
HM
SM2
SM3
SM1
HM
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Soft-macro Placement
Y
SM1
SM1
SM4
SM2
SM2
X
SM4
SM3
SM3
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The Experimental procedure Design Synthesis
Structural-tree Construction
SM Formation
Netlist
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The Experimental Procedure Floorplanning and PR
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The Experimental Procedure Timing Analysis
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Benchmarking Designs
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Results
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The Most Critical Path without Preserving Design
Hierarchy
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The Most Critical Path with Preserving Design
Hierarchy
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Resynthesis for Area/Delay Minimization
Resynthesis for area minimization
HM
SM1
SM2
SM3
Resynthesis for delay minimization
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Resynthesis-based Design Flow
P R
HDL Synthesis
Timing Analysis
Yes
OK?
Floorplanning
No
Resynthesis
SM Placement
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Slack Computation for Resynthesis Selection
p1
p2
FF
p3
Macro
NEG(SM_i) Slack(p_j), for all Slack(p_j) lt
0.
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The Experimental Design Flow
HDL Description
yes
no
Chip Layout
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Benchmarking Designs
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Results (Ind2 using 0.5 um tech.)
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Results (Ind2 using 0.25 um tech.)
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Results (Ave. Gate Delay VS. Interconnect Delay
of Ind2)
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The Initial Critical Path of Ind2 using the 0.5um
Library
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The Critical Path of Ind2 after 2 Resynthesis
Iterations
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Discussion

• How to perform timing analysis at different
  design stages?
• Timing, area and power budgeting methods for
  early design planning?
• Performance-driven and power-driven chip design
  methodologies.