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Team MUX

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Team MUX Adam Burton Mark Colombo David Moore Daniel Toler Introduction Overview (3) 16 Bit Master-Slave Rising edge registers using transmission gates ALU comprised ... – PowerPoint PPT presentation

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Title: Team MUX


1
Team MUX
  • Adam Burton Mark Colombo
  • David Moore Daniel Toler

2
Introduction
  • Overview
  • (3) 16 Bit Master-Slave Rising edge registers
    using transmission gates
  • ALU comprised of 5 functional blocks
  • Adder/Subtractor
  • And
  • Or
  • Shift
  • Multiplier

3
Team MUX- ALU Block
4
Adder/Subtractor Bitslice
  • In our Adder/Subtractor we had two bit slices
    with different inverting stages. This was so we
    could take advantage of the inversion property to
    cut down on the number of inverters in the carry
    path.

5
Shifter Bitslice
  • We used passgate logic because the reduced
    output swing was not an issue, and we could save
    area.

6
Functionality Plots
Pass c2c1c0001 A00gt1 Out00gt1
CLK
A0
A0
Out0
Out0
7
Functionality Plots
AND C2c1c0110 A01gt0 B00 Out01gt0
CLK
Out0
A0
Out0
A0
8
Functionality Plots
SUB c2c1c0011 A01 B01 Out00
CLK
A0,B0
A0,B0
Out0
Out0
9
Innovation
  • Sizing Strategy
  • What to size
  • How to size it
  • Design Trade-Offs
  • Arbitrary Function 16 bit multiplier

10
Sizing
  • Not on Critical Path ? Sized to conserve area
  • On Critical Path ? Sized for Delay
  • Attempted Logical Effort Calculations
  • Result Tapered Path for reduced delay
  • Optimized further through simulation
  • Buffers between registers and ALU

11
Trade-Offs
  • Considered Carry Look-ahead Adder
  • Additional area and power
  • Small benefit to delay
  • Supply Voltage
  • Higher ? Better Delay, More Power
  • Lower ? Worse Delay, Less Power
  • Decided on Delay due to being squared in metric,
    used 5V

12
Innovation in Multiplier
  • To produce a 16-bit output, need 8-bit multiplier
  • Team MUX Multiplier is 16 bits
  • Despite limited output width, offers more
    flexibility

13
Multiplier Attributes
  • The multiplier is a basic array-based multiplier.
  • Delay through the multiplier
  • Power consumption of the multiplier

14
Results
  • Worst case delay analyzed
  • 0x7FFF 0x0001 
  • Caused all bits to flip
  • Period 7ns
  • Frequency 143 MHz

15
Results
  • Area measurement
  • Counted up widths
  • Excluded buffers and multiplier
  • Width 4.211510-3 m

16
Results
  • Energy calculation
  • Cycle through all functions with alternating
    input
  • Integrated instantaneous power over period of
    operation
  • Energy 2.342610-9 J

17
Results
  • Final Metric
  • D2AE
  • Metric 4.84610-28 s2mJ

18
Conclusion
  • Meets or exceeds all specifications
  • Implements all functions
  • Low metric value
  • Multiplier is a valuable, common function

19
Questions?
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