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## Lecture 10 Sequential Logic

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### Lecture 10 Sequential Logic Prof. Sin-Min Lee Department of Computer Science San Jose State University D Flip-Flop with Reset T & J-K Flip-Flops Sequential Circuit ... – PowerPoint PPT presentation

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Title: Lecture 10 Sequential Logic

1
Lecture 10 Sequential Logic
CS147
• Prof. Sin-Min Lee
• Department of Computer Science
• San Jose State University

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D Flip-Flop with Reset
D Flip-Flop with Asynchronous Reset
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T J-K Flip-Flops
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Sequential Circuit
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Sequential Circuit (4)
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Sequential Circuit (6)
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Analysis of Sequential Circuit Logic Diagrams
Figure 8.8
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Timing Diagram for Figure 8.8 (a)
Figure 8.9
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State Table and State Diagram for Figure 8.8 (a)
Figure 8.10
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K-Maps for Circuit of Figure 8.8 (a)
Figure 8.11
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Synchronous Sequential Circuit with T Flip-Flop
-- Example 8.4
Figure 8.12
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Timing Diagram for Example 8.4
Figure 8.13
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State Table and State Diagram for Example 8.4
Figure 8.14
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K-Maps for Example 8.4
Figure 8.15
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Synchronous Sequential Circuit with JK Flip-flops
-- Example 8.5
Figure 8.16
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Timing Diagram and State Table for Example 8.5
Figure 8.17
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K-Maps for Example 8.5
Figure 8.18
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Generating the State Table From K-maps --
Example 8.5
Figure 8.19
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Synchronous Sequential Circuit Synthesis
Figure 8.20
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Introductory Synthesis Example -- Example 8.6
Figure 8.21
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Flip-flop Input Tables -- Example 8.6
Figure 8.22
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Generating the JK Flip-flop Excitation Maps
-- Example 8.7
Figure 8.23
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Clocked JK Flip-Flop Implementation -- Example 8.7
Figure 8.24
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Application Equation Method for Deriving
Excitation Equations -- Example 8.8
Figure 8.25
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Registers
• Two independent flip-flops with clear and preset

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Registers
• Missing Q, preset, clocks ganged
• Inversion bubbles cancelled, so loaded with
rising
• Can make 8- bit register with this