Combining Decomposition and Unfolding for STG Synthesis (application paper)

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Combining Decomposition and Unfolding for STG
Synthesis(application paper)

• Victor Khomenko1 and Mark Schaefer2
• 1School of Computing Science,
• Newcastle University, UK
• 2Institute of Computer Science,
• University of Augsburg, Germany

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Asynchronous circuits

• The traditional synchronous (clocked) designs
• lack flexibility to cope with contemporary
• design technology challenges
• Asynchronous circuits no clocks
• Low power consumption and EMI
• Tolerant of voltage, temperature and
• manufacturing process variations
• Modularity no problems with the clock skew
• and related subtle issues
• ITRS05 22 of designs will be driven by
  handshake clocking in 2013, and 40 in 2020
• Hard to synthesize efficient circuits
• The theory is not sufficiently developed
• Limited tool support

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Syntax-directed translation

• Idea
• Convert the specification to a network of
  standard handshake components (Balsa, Tangram)

• Computationally efficient
• Solution is guaranteed
• Produces highly over-encoded circuits, with large
  area and low performance

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Logic synthesis

• Idea
• Synthesize the circuit by exploring the state
  space of the specification

• Produces good circuits
• Solution is not guaranteed
• State space explosion synthesis based on state
  graphs is feasible only for small specifications
  (20-30 signals for BDD-based Petrify)

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Unfoldings

• Alleviate the state space explosion problem
• More visual than state graphs
• Proven efficient for model checking
• Can often synthesize specifications with 100-200
  signals
• Still not enough for real-life designs!

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Decomposition

• Idea
• Decompose the control path of the specification
  into smaller clusters and synthesize them
  one-by-one
• Use syntax-directed translation for clusters on
  which synthesis fails

• Can halve the area of the control path and
  improve its latency Carmona, Cortadella DAC06

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Example VME Bus Controller
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Initial partition

• Include signal triggers and choices
• lds dsr, ldtack, d
• d ldtack, dsr
• dtack d

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Initial decomposition
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Transition contraction
Merge similar components
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Resolving CSC conflicts
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Resolving CSC conflicts (contd)
dsr
lds
csc
lds-
d-
ldtack-
ldtack
dsr-
d
csc-
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Resulting Circuit
Data Transceiver
Device
Bus
d
lds
dtack
dsr
csc
ldtack
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Implementation
DESIJ
Large STGs(specification)
structural (approximate) tests
decomposition
unfolding-based (exact) tests
Medium STGs
PUNF
decomposition
MPSAT
Small STGs(components)?
synthesis
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Safeness-preserving contractions

• Unfolding is more efficient for safe nets
• Decomposition can create unsafe nets
• Contractions have to preserve safeness

t
Example
Structural condition
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Auto-conflicts

• Auto-conflicts appear if too many signals
  wereremoved
• Backtracking reinserts signals which remove the
  auto-conflict
• Unnecessary backtracking increases thefinal
  components

a
a
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Implicit places

• Implicit places are places the absence of tokens
  in which can never be the sole reason for some
  transition to be disabled
• Such places can be deleted without changing the
  behaviour of the STG
• Removing such places is essential for
  decomposition, because they can
• cause false alarms for other tests
• prevent contractions
• Structural test looks for a subset of implicit
  places (redundant places, shortcut places)

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Experimental results

• Large trees composed of alternating levels of
  sequencers and parallelisers were considered
• Intractable for stand-alone MPSAT and Petrify

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Experimental results
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Experimental results

• Outperforms stand-alone
• MPSAT and Petrify on large STGs
• Some intractable for
• stand-alone MPSAT and
• Petrify benchmarks were
• easily synthesized
• Huge STGs can be synthesized, e.g. SeqParTree-10
  with 12598 places, 8188 transitions, and 1025
  inputs and 3069 outputs was synthesized in less
  then 70 minutes

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• Thank you!
• Any questions?