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## ECE 425 - VLSI Circuit Design

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### ECE 425 - VLSI Circuit Design Lecture 6 - ASIC Design September 9, 2002 Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania 18042 – PowerPoint PPT presentation

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Title: ECE 425 - VLSI Circuit Design

1
ECE 425 - VLSI Circuit Design
• Lecture 6 - ASIC Design
• September 9, 2002

Prof. John Nestor ECE Department Lafayette
College Easton, Pennsylvania 18042 nestorj_at_lafayet
te.edu
2
Announcements
• Homework due Friday 2/18
• 2-2, 2-5, 2-6, 2-7, 2-8, 2-9, 2-12, 2-13, 2-20
• Problem 2-13 hints
• Assume VDD / p-transistors in top half,
• Gnd / n-transistors in bottom half
• Entrance Exam due Friday 2/18
• Wolf 2.1-2.6, 3.1-3.4
• Engineering Recruiting Day Fri. 4/1 in
• Submit resumes to Career Services by Feburary 25

3
Where we are...
• Last Time
• Layout
• Scaling
• Today
• Overview of Layout-Level Tools
• ASIC Design

4
Predicting future scaling - the ITRS
• ITRS International Technology Roadmap for
Semiconductors
• Sponsored by Semiconductor Industry Association
• Goal Forecast challenges in coming technology
nodes
• Overview WH Table 4.17

5
Review VLSI Levels of Abstraction
Specification (what the chip does, inputs/outputs)
Architecture major resources, connections
Register-Transfer logic blocks, FSMs, connections
Logic gates, flip-flops, latches, connections
Circuit transistors, parasitics, connections
6
Levels of Abstraction - Perspective
• Right now, were focusing on the low level
• Circuit level - transistors, wires, parasitics
• Layout level - mask objects
• Well work upward to higher levels
• Logic level - individual gates, latches,
flip-flops
• Register- transfer level
• Behavior level - specifications

7
The Challenge of Design
• Start higher level (specification)
• Finish lower level (implementation)
• Must meet design criteria and constraints
• Design time - how long did it take to ship a
product?
• Performance - how fast is the clock?
• Cost - NRE unit cost
• doing this successfully requires verification!

8
Layout-Level Design Tools
• Design Tools
• Schematic Editor (SUE)
• Layout Editor (MAGIC)
• Analysis Verification Tools
• Circuit Extractor (MAGIC)
• Circuit Simulator (Spice)
• Timing Simulator (IRSIM)
• Timing Analyzer
• Layout vs. Schematic (LVS) Equivalence Checker
(gemini)

9
• Layout Editors
• Design Rule Checkers (DRC)
• Circuit Extractors
• Layout vs. Schematic (LVS) Comparators
• Automatic Layout Tools
• Layout Generators
• ASIC Place/Route for Standard Cells, Gate Arrays

10
Layout Editors
• Goal produce mask patterns for fabrication
• Grid type
• Absolute grid (MAX, LASI, LEdit, Mentor
ICStation, other commercial tools)
• Magic lambda-based grid - easier to learn, but
less powerful
• Magic symbolic masks (layers combine to generate

11
Design Rule Checkers
• Goal identify design rule violations
• Often a separate tool (built in to Magic)
• General approach scanline algorithm
• Computationally intensive, especially for large
chips

12
Circuit Extractors
• Goal extract netlist of equivalent circuit
• Identify active components
• Identify parasitic components
• Capacitors
• Resistors

13
Layout Versus Schematic (LVS)
• Goal Compare layout, schematic netlists
• Compare transistors, connections (ignore
parasitics)
• Issue error if two netlists are not equivalent
• Important for large designs

14
Automatic Layout Tools
• Layout Generators - produce cell from spec.
• Simple Procedural specification of layout (see
book Fig. 2-35, p. 100)
• Complex Netlist - places wires individual
transistors
• Common generators
• Memory (RAM/ROM)
• Structured Logic (PLA)
• ASIC - Place, route modules with fixed shape
• Standard Cells - use predefined cells as "cookie
cutters"
• Gate Arrays - configurable pre-manufactured gates
• FPGAs - electrically configurable array of gates

15
ASICs - Application-Specific ICs
• Standard Cells
• Gate Arrays
• Field-Programmable Gate Arrays

16
Standard Cells
• All cells a fixed height (variable width)
• Provide Vdd, Gnd to lines to connect by abutment,
overlap
• Cells placed in rows by placement program
• Cells connected in channels by channel router

17
Standard Cell Layout
• Multiple metal layers allow over-the-cell routing
• Channels shrink or vanish in this case

18
Standard Cell Detail
19
Gate Arrays
• Completed array of gates without final metal
• Metal specified by CAD Tools
• faster turnaround
• lower NRE (non-recurring engineering) cost
• higher unit cost

20
Field-Programmable Gate Arrays (FPGAs)
• Fixed array of gates
• Electrically programmable interconnect
• Tradeoffs very low NRE, high unit cost

CLB
CLB
CLB
CLB
21
22
ASIC Economics
• Non-recurring Engineering (NRE) cost - up-front
cost of setting up manufacturing
• Unit cost - cost of each chip once production
begins

Total Cost
Volume
23
ASIC Trends - FPGAs vs. ASICs
• Standard cell NRE costs are rising rapidly
• FPGAs improving in size, performance, cost
• Will FPGAs supplant ASICs?

FPGA (current)
Total Cost
Volume
24
ASIC Trends - Perspectives
• The ASIC has been declared dead
• Rationale NRE costs are high, FPGAs more
cost-effective in all but high-volume cases
• This argument is very popular with FPGA vendors
• But, reports may be exaggerated!
• Many chips still designed with standard cells
• Current trend ASICs with IP blocks
• Current trend structured ASICs

25
Design with Intellectual Property (IP)
• Key Idea re-use predesigned components
• Hard IP - predesigned layout in a specific
technology
• Standard Cells
• Processor Cores
• Memory Cores
• Soft IP - synthesizeable HDL
• Proprietary algorithms (e.g. MPEG
encoding/decoding)

26
Structured ASICs
• Key idea provide a platform with many (but not
all) functions for a common application
• Network/Telecomm microprocessor, DSP,
serializer/deserializer
• Embedded Systems microcontroller, smart timer,
other peripherals
• Allow user to customize part of design to add
secret sauce
• FPGA Fabric - program in field
• Gate Array or Gate Array Like - customize with
metal layers only
• Important benefit lower NRE costs

27
Structured ASIC eaxmple
• LSI Logic RapidChip Platform (EE Times 9/9/02)
• Application-specific hard IP on pre-designed,
pre-manufactured chip
customize (maybe gate arrays arent dead after
all?)

28
• Extraction using Magic
• Simulation with IRSIM
• Switch-Level Simulator
• RC (t) timing model
• LVS using gemini

29
Lab 4 - Extraction
• in magic - extract creates filename.ext
• in shell - ext2sim filename creates filename.sim

30
Lab 4 - Simulation using IRSIM
• Starting IRSIM
• in shell - irsim ami.prm filename.sim
• Node values in simulation 0, 1, X, ...
• Some important commands
• analyzer net1 net2 trace signals in waveform
• h net set net to logic H
• l net set net to logic L
• vector vname net1 net2 group nets into bus
• set vname 001 set bus to value
• s time step simulation - time ns
• _at_ filename include command file
• q quit simulation

31
Lab 4 - LVS using Gemini
• Starting IRSIM
• in shell - gemini file1.sim file2.sim
• Where to get the files?
• file1.sim - generated by Sue sim it
• file2.sim - generated by extract, ext2sim

32
Coming Up
• Combinational Logic Design
• Gate Design Layout
• Delay
• Noise Margin
• Power Consumption
• A Mixed-Signal Digression D/A Converters